DS28CN01U+ MAXIM [Maxim Integrated Products], DS28CN01U+ Datasheet

no-image

DS28CN01U+

Manufacturer Part Number
DS28CN01U+
Description
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
www.maxim-ic.com
GENERAL DESCRIPTION
The DS28CN01 combines 1024 bits of EEPROM
with challenge-and-response authentication security
implemented
Publications (FIPS) 180-1/180-2 and ISO/IEC 10118-
3 Secure Hash Algorithm (SHA-1). The memory is
organized as four pages of 32 bytes each. Data
copy-protection and EPROM emulation features are
supported for each memory page. Each DS28CN01
has a guaranteed unique factory-programmed 64-bit
registration
DS28CN01 is accomplished through an industry
standard I²C- and SMBus™-compatible interface.
The SMBus timeout feature resets the device’s
interface if a bus-timeout fault condition is detected.
APPLICATIONS
Printed Circuit Board (PCB) Unique Serialization
Accessory and Peripheral Identification
Equipment Registration and License Management
Network Node Identification
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection
TYPICAL OPERATING CIRCUIT
Registers, Modes, and Commands are capitalized for
clarity.
SMBus is a trademark of Intel Corp.
V
CC
GND
µC
V
CC
SDA
SCL
number.
with
R
P
the
Communication
R
Federal
P
SDA
SCL
AD1
AD0 GND
DS28CN01
V
CC
Information
To additional
devices
with
Abridged Data Sheet
the
1 of 9
FEATURES
ORDERING INFORMATION
+ Denotes a lead-free package.
Request full data sheet at:
www.maxim-ic.com/fullds/DS28CN01
PIN CONFIGURATION
DS28CN01U+
DS28CN01U+T
1024 Bits of EEPROM Memory Partitioned
Into Four Pages of 256 Bits
Dedicated Hardware-Accelerated SHA Engine
for Generating SHA-1 MACs
EEPROM Memory Pages can be Individually
Copy-Protected or Put Into an EPROM Mode
(Program from 1 to 0 Only)
Write Access Requires Knowledge of the
Secret and the Capability of Computing and
Transmitting a 160-Bit MAC as Authorization
Unique, Factory-Programmed, and Tested
64-Bit Registration Number Assures Absolute
Traceability Because No Two Parts are Alike
Endurance 200k Cycles at +25°C
Serial Interface User Programmable for I²C
Bus and SMBus Compatibility
Supports 100kHz and 400kHz I²C
Communication Speeds
5.5V Tolerant Interface Pins
Operating Range: 1.62V to 5.5V,
-40°C to +85°C
8-Pin µSOP Package
PART
GND
AD0
AD1
NC
1
2
3
4
1Kbit I²C/SMBus EEPROM
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
µSOP
with SHA-1 Engine
DS28CN01
8 µSOP
8 µSOP
Tape-and-Reel
PIN-PACKAGE
8
7
6
5
REV: 061907
V
NC
SCL
SDA
CC

Related parts for DS28CN01U+

DS28CN01U+ Summary of contents

Page 1

... GND Registers, Modes, and Commands are capitalized for clarity. SMBus is a trademark of Intel Corp. Abridged Data Sheet FEATURES Information with the ORDERING INFORMATION DS28CN01U+ DS28CN01U+T To additional + Denotes a lead-free package. devices Request full data sheet at www.maxim-ic.com/fullds/DS28CN01 DS28CN01 SDA SCL PIN CONFIGURATION ...

Page 2

ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Maximum Current Any Pin Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. ...

Page 3

PARAMETER Input Capacitance SCL Clock Frequency Bus Timeout Hold-Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated. LOW Period of the SCL Clock (Note 13) HIGH Period of the SCL Clock Setup Time for a Repeated ...

Page 4

PIN DESCRIPTION PIN NAME Device Address Input Pin to Select the Slave Address. Sets slave address bits A1:A0; 1 AD0 must be tied to either GND, SDA, SCL Device Address Input Pin to Select the Slave Address. Sets ...

Page 5

DEVICE OPERATION Read and write access to the DS28CN01 is controlled through the I²C/SMBus serial interface. Since the DS28CN01 has memory areas and registers of different characteristics there are several special cases to consider. See the Read and Write section ...

Page 6

I²C/SMBus Protocol Data transfers can be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls the bus access, generates the START and STOP conditions, and determines the number of bytes transferred on the ...

Page 7

Acknowledged by Slave A slave device, when addressed, is usually obliged to generate an acknowledge after the receipt of each byte. The master must generate the clock pulse for each acknowledge bit. A slave that acknowledges must pull down the ...

Page 8

Application Information SDA and SCL Pullup Resistors SDA is an open-drain output on the DS28CN01 that requires a pullup resistor (Figure 6) to realize high logic levels. Because the DS28CN01 uses SCL only as input (no clock stretching), the master ...

Page 9

Figure 7. I²C Fast Speed Pullup Resistor Selection Chart 1200 1000 800 600 400 200 0 1.5 2 PACKAGE INFORMATION For the latest package outline information www.maxim-ic.com/DallasPackInfo. Mimimum Rp Max. Load at Min. Rp fast mode 2.5 3 ...

Related keywords