DS28CN01U+ MAXIM [Maxim Integrated Products], DS28CN01U+ Datasheet - Page 5

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DS28CN01U+

Manufacturer Part Number
DS28CN01U+
Description
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
DEVICE OPERATION
Read and write access to the DS28CN01 is controlled through the I²C/SMBus serial interface. Since the
DS28CN01 has memory areas and registers of different characteristics there are several special cases to consider.
See the Read and Write section for details.
Serial Communication Interface
General Characteristics
The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no
communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain
or open-collector to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the
Standard-mode, up to 400kbps in the Fast-mode. The DS28CN01 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” The DS28CN01 is a slave device.
Slave Address/Direction Byte
To be individually accessed, each device must have a slave address that does not conflict with other devices on
the bus. The slave address to which the DS28CN01 responds is shown in Figure 1. The slave address is part of
the slave-address/direction byte. The upper 3 bits of the slave address of the DS28CN01 are set to 101b. The AD0
pin controls address A0 and A1; AD1 controls A2 and A3. AD0 and AD1 can be tied to GND, V
Table 1 shows the translation of these four pin states to binary addresses. To be selected the device must be
addressed with A0 to A3 matching the binary address of the respective pins.
Figure 1. DS28CN01 Slave Address
Table 1. Pin State to Binary Translation
The last bit of the slave-address/direction byte (R/W) defines the data direction. When set to a 0, subsequent data
flows from master-to-slave (Write-Access Mode); when set to a 1, data flows from slave-to-master (Read-Access
Mode).
GND
AD1
SDA
SCL
V
CC
A3
0
0
1
1
A2
0
1
0
1
Most Significant Bit
A6
1
GND
AD0
SDA
SCL
V
CC
A5
0
7-Bit Slave Address
A1
A4
0
0
1
1
1
A3
5 of 9
4-Level Pin States
A0
AD1
0
1
0
1
See Text
A2
A1
AD0
A0
Read or Write
Determines
R/W
CC
, SCL, or SDA.

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