DS28CN01U+ MAXIM [Maxim Integrated Products], DS28CN01U+ Datasheet - Page 3

• Manufacturer Part Number: DS28CN01U+
• Manufacturer: MAXIM [Maxim Integrated Products]

Input Capacitance
SCL Clock Frequency
Bus Timeout
Hold-Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
LOW Period of the SCL Clock
(Note 13)
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
(Notes 14, 15)
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
PARAMETER
Specifications at -40°C are guaranteed by design and characterization only and not production tested.
Guaranteed by design, characterization and/or simulation only, and not production tested.
This specification is valid for each 8-byte memory row.
Write-cycle endurance is degraded as T
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
All values are referred to V
C
Specification v2.1 are allowed.
The DS28CN01 does not obstruct the SDA and SCL lines if V
The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 and SCL stays at the same logic level
or SDA stays low for this interval, the DS28CN01 behaves as though it has sensed a STOP condition.
System requirement.
The DS28CN01 provides a hold time of at least 300ns for the SDA signal (referred to the V
undefined region of the falling edge of SCL.
The master can provide a hold time of 0ns minimum when writing to the device. This 0ns minimum is guaranteed by design,
characterization and/or simulation only, and not production tested.
A Fast-Mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
(according to the Standard-mode I²C-bus specification) before the SCL line is released.
B
= total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall-times according to I²C-Bus
IHmin
SYMBOL
t
TIMEOUT
t
t
t
t
t
and V
HD:STA
HD:DAT
SU:DAT
SU:STO
SU:STA
t
A
t
f
t
HIGH
LOW
C
SCL
BUF
C
increases.
B
I
ILmax
A
increases.
levels.
(Note 2)
(Note 12)
(Note 12)
(Note 13)
V
V
V
(Note 13)
(Note 13)
V
V
V
(Notes 2, 13, 16)
(Note 13)
(Note 13)
(Notes 2, 13)
CC
CC
CC
CC
CC
CC
≥ 2.7V
≥ 2.0V
< 2.0V
≥ 2.7V
≥ 2.0V
< 2.0V
CONDITIONS
3 of 9
CC
is switched off.
MIN
Rmax
100
0.6
1.3
1.5
1.9
0.6
0.6
0.3
0.3
0.3
0.6
1.3
25
+ t
SU:DAT
IHmin
TYP
= 1000 + 250 = 1250ns
of the SCL signal) to bridge the
SU:DAT
≥ 250ns must then be
MAX
400
400
0.9
1.1
1.5
10
75
UNITS
kHz
ms
pF
µs
µs
µs
µs
µs
µs
µs
pF
ns