DS28CN01U+ MAXIM [Maxim Integrated Products], DS28CN01U+ Datasheet - Page 6

• Manufacturer Part Number: DS28CN01U+
• Manufacturer: MAXIM [Maxim Integrated Products]

I²C/SMBus Protocol
Data transfers can be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls
the bus access, generates the START and STOP conditions, and determines the number of bytes transferred on
the data line (SDA) between START and STOP. Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
During any data transfer, SDA must remain stable whenever the clock line is HIGH. Changes in SDA line while
SCL is high are interpreted as a START or a STOP. The protocol is illustrated in Figure 2. See Figure 3 for detailed
timing references .
Figure 2. I²C/SMBus Protocol Overview
Bus Idle or Not Busy
Both SDA and SCL are inactive, i.e., in their logic HIGH states.
START Condition
To initiate communication with a slave the master must generate a START condition. A START condition is defined
as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition
To end communication with a slave the master must generate a STOP condition. A STOP condition is defined as a
change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition
Repeated starts are commonly used for read accesses after having specified a memory address to read from in a
preceding write access. The master can use a repeated START condition at the end of a data transfer to
immediately initiate a new data transfer following the current one. A repeated START condition is generated the
same way as a normal START condition, but without a preceding STOP condition.
Data Valid
With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (t
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
t
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
SU:DAT
SDA
SCL
+ t
Idle
R
in Figure 3) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
Condition
START
HD:DAT
MS-bit
1
after the falling edge of SCL and t
Slave Address
2
6
7
R/W
Acknowledgment
8
from Receiver
6 of 9
ACK
ACK
bit
9
SU:DAT
1
before the rising edge of SCL, see Figure 3).
Repeated if more bytes
2
are transferred
8
ACK
ACK
bit
9
STOP Condition
Repeated START
Condition