DS26303G-120 MAXIM [Maxim Integrated Products], DS26303G-120 Datasheet - Page 49
DS26303G-120
Manufacturer Part Number
DS26303G-120
Description
3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.DS26303G-120.pdf
(97 pages)
- Current page: 49 of 97
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 5 to 3: Transmit Error-Insertion Rate (TEIR[2:0]). These bits indicate the rate at which errors are inserted in
the output data stream. One out of every 10
disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A TEIR[2:0]
value of 2 result in every 100th bit being inverted. Error insertion starts when this register is written to with a
TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process, the new
error rate will be started after the next error is inserted.
Bit 2: Bit-Error-Insertion Enable (BEI). When 0, single bit-error insertion is disabled. When 1, single bit-error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit-error insertion is enabled. A 0-to-1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error is
inserted.
Bit 0: Manual-Error Insert-Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual-error-insertion signal (TMEI). Note: If TMEI or TSEI is 1,
changing the state of this bit may cause a bit error to be inserted.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Performance-Monitoring Update Status (PMS). This bit indicates the status of the receive performance-
monitoring register (counters) update. This bit transitions from low to high when the update is completed. PMS is
asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM = 1) goes low.
Bit 1: Bit Error Count (BEC). When 0, the bit error count is 0. When 1, the bit error count is 1 or more.
Bit 0: Out of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
—
—
7
0
7
0
—
—
6
0
6
0
TEICR
Transmit Error-Insertion Control Register
08h
BSR
BERT Status Register
0Ch
TEIR2
—
5
0
5
0
n
bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value of 0
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TEIR1
49 of 97
—
4
0
4
0
TEIR0
PMS
3
0
3
0
BEI
—
2
0
2
0
TSEI
BEC
1
0
1
0
MEIMS
OOS
0
0
0
0
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