DS26303G-120 MAXIM [Maxim Integrated Products], DS26303G-120 Datasheet - Page 13

• Manufacturer Part Number: DS26303G-120
• Description: 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
• Manufacturer: MAXIM [Maxim Integrated Products]

RLOS1/TECLK
RXPROBEC1
RXPROBEA1
RXPROBEB1
RNEG6/CV6
RNEG7/CV7
RNEG8/CV8
scan_clk
scan_do
RLOS2/
RLOS3/
RLOS4/
RLOS5/
RLOS6/
scan_di
RLOS7/
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
NAME
MCLK
eLQFP
105
141
110
103
143
113
106
39
32
78
71
10
42
35
75
68
4
6
3
PIN
PBGA
C12
M14
C14
P14
A14
K12
K11
E11
E12
M1
C3
C1
A3
P1
A1
E1
K4
K3
E3
tri-state
TYPE
I/O
I/O
I/O
O,
O
O
I
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
excessive zeros are reported by driving CVn high for one clock
cycle. If HDB3 or B8ZS is not selected, this pin indicates only
BPVs.
Note: During an RLOS condition the output remains active.
Receive Clock for Channel 1 to 8. The receive data
RPOS/RNEG or RDAT is clocked out on the rising edge of RCLK.
RCLK output can be inverted. If a given receiver is in power-down
mode, the RCLK is high impedance.
Master Clock. This is an independent free-running clock that can
be a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz
±50ppm for T1 mode. The clock selection is available by
MPS0, MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be
internally adapted to 1.544MHz and a multiple of 1.544MHz can
be internally adapted to 2.048MHz. In hardware mode, internal
adaptation is not available so the user must provide 2.048MHz
±50ppm for E1 mode or 1.544MHz ±50ppm for T1 mode.
Loss-of-Signal Output/T1-E1 Clock
RLOS1: This output goes high when there is no transition on the
received signal over a specified interval. The output goes low
when there is sufficient ones density in the received signal. The
RLOS criteria for assertion and desertion criteria are described in
the Functional Description section. The RLOS outputs can be
configured to comply with T1.231, ITU G.775, or ETSI 300 233. In
hardware mode, ETSI 300 233 “RLOS Criteria” is not available.
TECLK: When enabled by register MC, this output becomes a T1-
or E1-programmable clock output. For T1 or E1 frequency
selection, see register CCR. This option is not available in
hardware mode.
Loss-of-Signal Output/Receive Probe
RLOS[2:4]: See RLOS1 pin description.
RXPROBE A1, B1, C1: Used in test only.
Loss-of-Signal Output/Scan Data Output
RLOS5: See RLOS1 pin description.
scan_do: Data output during scan.
Loss-of-Signal Output/Scan Data Input
RLOS6: See RLOS1 pin description.
scan_di: Data input during scan.
Loss-of-Signal Output/Scan Clock
RLOS7: See RLOS1 pin description.
scan_clk: Clock input during scan.
13 of 97
FUNCTION
MC
bits