DS26303G-120 MAXIM [Maxim Integrated Products], DS26303G-120 Datasheet - Page 45

• Manufacturer Part Number: DS26303G-120
• Description: 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
• Manufacturer: MAXIM [Maxim Integrated Products]

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLK for channel n is
disabled upon a loss of signal and set as a low output. When reset or default, RCLK switches to MCLK upon a loss
of signal within 10ms.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: INT Pin Mode (INTM). This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
Bit 0: Clear-On-Write Enable (CWE). When this bit is set, the clear-on-write is enabled for all the latched interrupt
status registers. The host processor must write a 1 to the latched interrupt status register bit position before the
particular bit is cleared. Default for all the latched interrupt status registers is to clear on a read.
0 = Pin is high impedance when not active.
1 = Pin drives high when not active.
RDULR8
—
7
0
7
0
RDULR7
—
6
0
6
0
RDULR
RCLK Disable Upon LOS Register
16h
GISC
Global Interrupt Status Control
1Eh
RDULR6
—
5
0
5
0
RDULR5
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
45 of 97
—
4
0
4
0
RDULR4
—
3
0
3
0
RDULR3
—
2
0
2
0
RDULR2
INTM
1
0
1
0
RDULR1
CWE
0
0
0
0