DS26303G-120 MAXIM [Maxim Integrated Products], DS26303G-120 Datasheet - Page 17

• Manufacturer Part Number: DS26303G-120
• Description: 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
• Manufacturer: MAXIM [Maxim Integrated Products]

A4/RIMPMSB
A3/GMC3
A2/GMC2
A1/GMC1
A0/GMC0
VDDIO
JTRSTB
VSSIO
NAME
DVDD
DVSS
CLKE
JTCLK
JTMS
JTDO
OE
JTDI
eLQFP
17, 92
18, 91
114
115
12
13
14
15
16
19
20
95
96
97
98
99
PIN
PBGA
G12
G14
G11
E14
E13
F11
F14
F13
F12
G1,
G4,
G3
H1
H4
F4
F3
F2
F1
I, pullup
I, pullup
I, pullup
high-Z
TYPE
O,
—
—
—
—
I
I
I
I
POWER SUPPLIES
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Address Bus 4–0/G.772 Monitoring Control/Rx Impedance
Mode Select
A[4:0]: These five pins are address pins in parallel host mode. In
serial host mode and multiplexed host mode, these pins should be
grounded.
RIMPMSB: In hardware mode when this pin is low, the internal
impedance mode is selected, so RTIP and RING require no
external resistance component. When high, external impedance
mode is selected so RTIP and RING require external resistance.
GMC[3:0]: In hardware mode, these signal pins are used to select
transmitter or receiver for nonintrusive monitoring. Receiver 1 is
used to monitor channels 2 to 8 of one receiver from RTIP2–
RTIP8/RRING2–RRING8 or one transmitter from TTIP2–
TTIP8/TRING2–TRING8. These signal pins correspond to the bits
in
Output Enable. If this pin is pulled low, all the transmitter outputs
(TTIP and TRING) are high impedance. Additionally, the user may
use this same pin to turn off all the impedance matching for the
receivers at the same time if register bit
Clock Edge. When CLKE is high, SDO is valid on the falling edge
of SCLK. When CLKE is low SDO is valid on the rising edge of
SCLK. When CLKE is high, the RCLK for all the channels is
inverted. This aligns RPOS/RNEG on the falling edge of RCLK
and overrides the settings in register RCLKI. When low,
RPOS/RNEG is aligned on the settings in register RCLKI.
JTAG Test Port Reset. This pin if low resets the JTAG port. If not
used it can be left floating.
JTAG Test Mode Select. This pin is clocked on the rising edge of
JTCLK and is used to control the JTAG selection between scan
and test machine control.
JTAG Test Clock. The data JTDI and JTMS are clocked on rising
edge of JTCLK and JTDO is clocked out on the falling edge of
JTCLK.
JTAG Test Data Out. This is the serial output of the JTAG port.
The data is clocked out on the falling edge of JTCLK.
Test Data Input. This pin input is the serial data of the JTAG test.
The data on JTDI is clocked on the rising edge of JTCLK. This pin
can be left unconnected.
3.3V Digital Power Supply
Digital Ground
3.3V I/O Power Supply
I/O Ground
17 of 97
Table
JTAG
5-9.
FUNCTION
GMR.RHPMC
is set.