ch7304 Chrontel, ch7304 Datasheet - Page 4

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
1.2
4
Pin #
1
2
3,4,6,7,9,10,
12,13,15,16
20, 21
17,23,26,29
18,24,27,30
32
33
34
37
39
40
41
43
44
45
46
47
Table 1: Pin Description
Pin Description
# of Pins Type
1
1
10
2
4
4
1
1
1
1
1
1
1
1
1
1
1
1
Out
Out
Out
Out
Out
In
Out
In
Analog
In/Out
In
In/Out
In
In
In
In
In
-
Symbol
ENABLK
ENAVDD
NC
LLC, LLC*
LDC[3:0]
LDC[3:0]*
VSWING
XO
XI
LPLL_CAP
CONFIG
SPC
SPD
V
H
VREF
DE
RESET*
Description
Back Light Enable
Enable Back-Light of LCD Panel. Output is driven from 0 to DVDD.
Panel Power Enable
Enable panel VDD. Output is driven from 0 to DVDD.
No Connect
LVDS Differential Clock
Positive LVDS differential data[3:0]
Negative LVDS differential data [3:0]
LVDS Voltage Swing Control
This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor
should be connected between this pin and LGND (pin 31) using short and
wide traces.
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XI. However, if an external CMOS clock is attached
to XI, XO should be left open.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XO. However, an external CMOS compatible clock
can drive the XI input.
LVDS PLL Capacitor
This pin allows coupling of any signal to the on-chip loop filter capacitor.
Configure / Output
This pin configures the device ID.
Serial Port Clock Input
This pin functions as the clock input of the serial port and can operate with
inputs from 1.1V ~ 3.3V. The serial port address of the CH7304 is 75h. For
more details on CH7304 serial port read/write operations, please refer to
AN61.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and can
operate with inputs from 1.1V ~ 3.3V. Outputs are driven from 0 to VDDV.
The serial port address of the CH7304 is 75h. For more details on CH7304
serial port read/write operations, please refer to AN61.
Vertical Sync Input
This pin accepts a vertical sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF signal is the threshold level.
Horizontal Sync Input
This pin accepts a horizontal sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF is the threshold level for this input.
Reference Voltage Input
The VREF pin inputs a reference voltage of VDDV / 2. The signal is
derived externally through a resistor divider and decoupling capacitor, and
will be used as a reference level for data, sync and clock inputs.
Data Enable
This pin accepts a data enable signal which is high when active video data
is input to the device, and remains low during all other times. The levels
are 0 to VDDV. VREF is the threshold level.
Reset * Input (Internal Pull-up)
When this pin is low, the device is held in the power on reset condition.
When this pin is high, reset is controlled through the serial port.
201-0000-053
Rev. 1.31,
CH7304
6/14/2006