ch7304 Chrontel, ch7304 Datasheet

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... VREF 201-0000-053 Rev. 1.31, 6/14/2006 General Description The CH7304 is a Display Controller device, which accepts a graphics data stream over one 12-bit wide variable voltage (1.1V to 3.3V) port. The data stream outputs through an LVDS transmitter to an LCD panel. A maximum of 100M pixels per second can be output through a single LVDS link ...

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... Control Registers Description____________________________________________________________ 14 3.3 Control Registers Description____________________________________________________________ 15 3.4 Recommended Settings_________________________________________________________________ 25 4.0 Electrical Specifications __________________________________________________________________ 26 4.1 Absolute Maximum Ratings _____________________________________________________________ 26 4.2 Recommended Operating Conditions ______________________________________________________ 26 4.3 Electrical Characteristics _______________________________________________________________ 26 4.4 Digital Inputs / Outputs_________________________________________________________________ 27 4.5 AC Specifications _____________________________________________________________________ 27 4.6 Timing Information ___________________________________________________________________ 29 5.0 Package Dimensions_____________________________________________________________________ 31 6.0 Revision History ________________________________________________________________________ 32 1.0 2 Table of Contents 201-0000-053 CH7304 Rev. 1.31, 6/14/2006 ...

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... NC 5 LVDD LGND LVDD LGND 201-0000-053 Rev. 1.31, 6/14/2006 Chrontel CH7304 Figure 2: 64 Pin LQFP Package (Top View) CH7304 48 VDDV 47 RESET VREF DVDD 41 SPD 40 SPC 39 CONFIG 38 LPLL_VDD 37 LPLL_CAP 36 LPLL_GND 35 DGND 34 XI ...

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... This pin configures the device ID. Serial Port Clock Input This pin functions as the clock input of the serial port and can operate with inputs from 1.1V ~ 3.3V. The serial port address of the CH7304 is 75h. For more details on CH7304 serial port read/write operations, please refer to AN61. ...

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... H, V and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The clock polarity can be Register 1Ch selected by the MCP control bit ( Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (1.1V to 3.3V) LVDS Supply Voltage (3.3V) LVDS Ground LVDS PLL Supply Voltage (3.3V) LVDS PLL Ground CH7304 ). 5 ...

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... DDR). For the multiplexed data, clock at 2X pixel rate the data applied to the CH7304 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is programmable ...

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... Input Data Formats The CH7304 supports 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on both clock edges clock latching data with a single edge (rising or falling depending on the value of the MCP bit – rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). Received data is formatted and sent through an internal data bus P[23:0] to the LVDS data path ...

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... P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7304 1 RGB 8-8-8 (2x12-bit) or RGB 5-6-5 (2x8-bit) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 (2x8-bit) P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a ...

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... HSYNC HSYNC VSYNC VSYNC N/A N/A CH7304 18-bit HSYNC VSYNC DE N/A N/A N/A N/A N/A N/A N/A 9 ...

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... CHRONTEL 2.2.2 Dithering The CH7304 has a dither engine that can convert the 24-bit pixel data to 18-bit pixel data for better image quality on 18- bit panels. Maximum pixel rate supported is 100M Pixels / sec. 2.2.3 Power Sequencing The CH7304 conforms to SPWG’s requirements on power sequencing. The timing specification shown in Figure superset of the requirements dictated by the SPWG specification ...

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... LPFORC LPLEN Register 66h Note: 1) LOCKST will be logic PANEN low if either XCLK or the LSYNCEN LVDS PLL output is LPLOCK unstable. LPFORC 2) SYNCST will be logic LPLEN low if either Hsync or BKLEN Vsync is unstable or SYNCST missing. CLKDETD Reg. 14h [2] Power Sequencing CH7304 0 MUX 1 ENAVDD ENABKL 11 ...

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... For further details, please contact Chrontel Applications Group. 2.3 Power Down The CH7304 can be powered down via software control to achieve very low standby current. For a complete description of each individual bit please refer to the appropriate register description in Registers 63h and 76h. 12 CH7304 201-0000-053 Rev ...

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... CHRONTEL 3.0 Register Control The CH7304 is controlled via a serial port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device should retain all register values during power down modes ...

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... LPPSD0 LPVCO3 Reserved LDEN1 LDEN0 Reserved Reserved Reserved Reserved Reserved Reserved LPLF1 LPLF0 LPPDN LPLF3 LPPD4 LPPD3 BGLMT5 BGLMT4 BGLMT3 CH7304 76h 78h 66h 78h 76h 76h 72h 72h 66h 64h 66h Bit 2 Bit 1 Bit 0 CLKDETD Reserved Reserved MCP Reserved XCM ...

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... Section 4.5. STEP 201-0000-053 Rev. 1.31, 6/14/2006 CLKDETD R/W R/W R R/W R/W R XCMD3 XCMD2 XCMD1 XCMD0 R/W R/W R CH7304 Symbol: CDD Address: 14h Reserved Reserved R/W R/W R Symbol: CM Address: 1Ch MCP Reserved XCM R/W R/W R Symbol: IC Address: ...

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... XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP R/W R/W R Table 9: D[11:0] Input Buffer Type Selection CH7304 Symbol: IDF Address: 1Fh IDF2 IDF1 IDF0 R/W R/W R 201-0000-053 Rev. 1.31, 6/14/2006 ...

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... R/W R Reserved ResetIB ResetDB R/W R/W R Table 10: Test Pattern Selection Test Pattern No test pattern – Input data is used Color Bars Horizontal Luminance Ramp Black screen CH7304 Symbol: CSC Address: 31h RGB R/W R/W R Symbol: STP Address: 48h Reserved TSTP1 ...

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... CHRONTEL Version ID Register BIT SYMBOL: VID7 VID6 TYPE DEFAULT Register VID is a read only register containing the version ID number of the CH7304 family. Product Number CH7304 Device ID Register BIT SYMBOL: DID7 DID6 TYPE DEFAULT Register DID is a read only register containing the device ID number of the CH7304 the state of the CONFIG pin, pin39 (bit 5 and bit 0 of register 4Bh will update accordingly) ...

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... Select LPFORC (Lock detect sentry is overridden if LPFORC is set to ‘1’) 201-0000-053 Rev. 1.31, 6/14/2006 Reserved LVDS24 LDD R/W R/W R BKLEN LPLEN LPFORC LPLOCK LSYNCEN PANEN R/W R/W R CH7304 Symbol: LVDSE Address: 64h Reserved LDI LEOSWP R/W R/W R Symbol: LPMC Address: 66h R/W ...

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... TP0FF8 TPBLD6 TPBLD5 TPBLD4 TPBLD3 TPBLD2 TPBLD1 TPBLD0 TYPE: R/W R/W DEFAULT TPON5 TPON4 TPON3 R/W R/W R R/W R/W R R/W R/W R 201-0000-053 CH7304 Symbol: PST1 Address: 67h TPON2 TPON1 TPON0 R/W R/W R Symbol: PST2 Address: 68h R/W R/W R Symbol: PST3 Address: 69h R/W R/W ...

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... TPOFF5 TPOFF4 TPOFF3 TPOFF2 TPOFF1 R/W R/W R TPPWD5 TPPWD4 TPPWD3 TPPWD2 TPPWD1 TPPWD0 R/W R/W R LPFFD1 LPFFD0 LPFBD3 LPFBD2 LPFBD1 R/W R/W R CH7304 Symbol: PST4 Address: 6Ah TPOFF0 R/W R/W R Symbol: PST5 Address: 6Bh R/W R/W R Symbol: LPFBDC ...

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... Description 0 LVDS Output Drivers disabled 1 LVDS Output Drivers enabled LPPSD1 LPPSD0 LPVCO3 LPVCO2 LPVCO1 LPVCO0 R/W R/W R Reserved Reserved LDENO R/W R/W R CH7304 Symbol: LPVC Address: 72h R/W R/W R Symbol: OUTEN Address: 73h LPCP2 LPCP1 LPCP0 R/W R/W R 201-0000-053 Rev ...

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... Rev. 1.31, 6/14/2006 Reserved Reserved Reserved R/W R/W R LODA0 Output Driver Amplitude (mV) 0 305 1 285 0 265 1 245 0 225 1 410 0 370 1 330 R/W R/W R CH7304 Symbol: LODA Address: 74h LODA2 LODA1 LODA0 R/W R/W R Symbol: LST Address: 75h R/W R/W R ...

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... Enable FIFO Reset = 1 => Normal Operation LPLF1 LPLF0 LPPDN R/W R/W R LPLF0 PLL Loop Filter Resistor Value (Ohm) 0 1800 2600 1 1000 0 3200 1 0 21,800 1 42,600 11,000 0 73,200 1 CH7304 Symbol: LPD Address: 76h LPPRB Reserved LODPDB0 R/W R/W R 201-0000-053 Rev. 1.31, 6/14/2006 ...

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... LPLF3 LPPD4 LPPD3 R/W R/W R R/W R/W R 1280 x 1024 ADh A3h ADh ADh C8h DBh F6h F6h ADh AFh 80h 80h 10h 10h CH7304 Symbol: LVCTL Address: 78h LPPD2 LPPD1 LPPD0 R/W R/W R Symbol: BGLMT Address: 7Fh R/W R/W R ...

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... LVDS output @ 65 MHz I VDDV (1.8V) current (15pF load) VDDV I Total Power Down Current PD 26 Min -0.5 GND – 0.5 -65 Min 3.1 3.1 3.1 3.1 1.1 = 0°C – 70°C, VDD =3.3V ± 5%) A Min CH7304 Typ Max Units 5.0 VDD + 0.5 Indefinite Sec ° °C 150 °C 150 °C 260 °C 245 °C 225 ...

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... GND-0 0 -0.4mA VDD-0 3.2mA OL Test Condition Min 25 6. < 1.2ns XCLK = XCLK* to 0.5 D[11:0 Vref D[11:0 0.5 Vref to XCLK = XCLK* 50 CH7304 Typ Max Unit 0.4 V VDD + 0 DVDD+0.5 V Vref-0.25 V VDD + 0 0.2 V Typ Max Unit 165 MHz 40 ns ...

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... V SWING 100Ω and 5pF differential load 80% -> 20% V SWING 100Ω and 5pF differential load for single channel operation. Dual channel operation is required for XCLK 201-0000-053 CH7304 Typ Max Unit 453 mV 453 1.375 V 1.375 ...

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... Fall time Jitter peak to peak j Note 1: Maximum jitter with EMI reduction turned off. 201-0000-053 Rev. 1.31, 6/14/2006 0.8 V swing - Figure 7: AC Timing for LVDS Outputs CH7304 V ring +/-20% V swing Differential 0.2 V swing t f Min Typ Max see section 4.6 see section 4.6 see section 4 ...

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... Hold Time: D[11:0 and DE to XCLK, XCLK XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0 & DE rise/fall time w/ 15pF load PIXELS t2 1 VGA Line t2 CH7304 P0a P0b P1a P1b P2a P2b Min Typ Max see Section 4.5 see Section 4.5 1 ...

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... Package Dimensions Table of Dimensions No. of Leads Milli- MIN 12 10 meters MAX 201-0000-053 Rev. 1.31, 6/14/2006 SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 Figure 9: 64 Pin LQFP Package CH7304 LEA D CO- PLANARITY H .004 “ 0.45 0.09 0° 1.00 0.75 0.20 7° 31 ...

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... Renamed GPIO pin to CONFIG 2. Renamed LL1C and LL1C* to LLC and LLC* 3. Removed LDC[7:4], LDC*[7:4], LL2C, and LL2C* Added Ordering Information Added lead free and tape & reel order information Corrected part number of lead free and tape & reel. CH7304 201-0000-053 Rev. 1.31, 6/14/2006 ...

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... Rev. 1.31, 6/14/2006 Disclaimer ORDERING INFORMATION Package Type Number of Pins LQFP 64 LQFP, 64 Tape&Reel LQFP, Lead free 64 LQFP, Lead free, 64 Tape&Reel Chrontel 2210 O’Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7304 Voltage Supply 3.3V 3.3V 3.3V 3.3V 33 ...