ch7304 Chrontel, ch7304 Datasheet - Page 25

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
LVDS Control
LPPD[4:0] (bits 4-0) of Register LVCTL define the LVDS PLL Phase Detector Control. The recommended settings are
shown in Table 15 in Section 0.
LPLF[4:3] (bits 6-5) of Register LVCTL control the LVDS PLL Loop Filter Capacitor. The recommended settings are
shown in Table 15 in Section 0.
LPCP3 (bit 7) of Register LVCTL enables the LVDS PLL Static Phase Error Reduction. The default value is
recommended.
Bang Limit Control
This register limits the allowable occurrences of internal LVDS FIFO over and under-runs within one VGA frame.
The recommended setting is shown in Table 15 in Section 0.
The recommended values for the LVDS PLL are shown in Table 15 below.
201-0000-053
Address/Bit
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
Recommended Settings
Table 15: LVDS Control Settings
LPCP3
7Fh
71h
72h
73h
74h
76h
78h
TYPE:
TYPE:
BIT:
BIT:
BGLMT7 BGLMT6 BGLMT5 BGLMT4 BGLMT3 BGLMT2 BGLMT1 BGLMT0
= 0 =>
= 1 =>
LPCP3
R/W
R/W
800 x 600
Rev. 1.31, 6/14/2006
0
0
7
7
ADh
ADh
ADh
C8h
F6h
80h
10h
Static Phase Error Reduction Disabled
Static Phase Error Reduction Enabled
LPLF4
R/W
R/W
6
0
6
0
1024 x 768
ADh
ADh
ADh
C8h
F6h
80h
10h
LPLF3
R/W
R/W
5
1
5
0
1280 x 1024
ADh
DBh
AFh
A3h
LPPD4
F6h
80h
10h
R/W
R/W
1
4
4
1
LPPD3
R/W
R/W
3
1
3
0
Symbol:
Address:
Symbol:
Address:
LPPD2
R/W
R/W
2
0
2
0
LPPD1
R/W
R/W
LVCTL
78h
BGLMT
7Fh
1
0
1
0
CH7304
LPPD0
R/W
R/W
0
0
0
0
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