ch7304 Chrontel, ch7304 Datasheet - Page 21

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
TPBLD[6:0] (bits 6-0) of Register PST3 define the Back Light Disable time (T3), the required time after disabling the
back light before the valid LVDS Clock and Data become tri-stated or disabled. Refer to Figure 5 and Table 6 in
Section 2.2.3. The range of T3 is 2ms to 256ms in increments of 2ms.
TPOFF8 (bit 7) of Register PST3 defines the MSB of the Power Off time (T4). The entire bit field, TPOFF[8:0], is
comprised of this bit, TPOFF8, plus TPOFF[7:0] contained in the Power Sequencing T4 register (Register 6Ah). Refer
to the description of the PST4 register (Register 6Ah) for more information.
Power Sequencing T4
Register PST4 defines the Power Off time (T4), the required time prior to power off after the valid LVDS Clock and
Data become tri-stated or disabled. The entire bit field, TPOFF[8:0], is comprised of these bits, TPOFF[7:0], plus
TPOFF8 contained in the Power Sequencing T3 register (Register 69h, bit 7). Refer to Figure 5 and Table 6 in
Section 2.2.3.
The range is 2ms to 512ms in increments of 1ms.
Power Sequencing T5
TPPWD[5:0] (bits 5-0) of Register PST5 define the Power Cycle time (T5), the waiting time required prior to enabling
power on after power has been off. Refer to Figure 5 and Table 6 in Section 2.2.3. The range is 2ms to 1600ms in
increments of 50ms.
LVDS PLL Feed Back Divider Control
201-0000-053
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
Reserved Reserved
Reserved Reserved
TPOFF7 TPOFF6
R/W
R/W
R/W
Rev. 1.31, 6/14/2006
0
1
1
7
7
7
R/W
R/W
R/W
6
0
6
1
6
0
TPPWD5 TPPWD4 TPPWD3 TPPWD2 TPPWD1 TPPWD0
LPFFD1 LPFFD0 LPFBD3 LPFBD2 LPFBD1
TPOFF5 TPOFF4 TPOFF3 TPOFF2 TPOFF1
R/W
R/W
R/W
5
0
5
1
5
0
R/W
R/W
R/W
4
0
4
0
4
0
R/W
R/W
R/W
3
0
3
0
3
0
Symbol:
Address:
Symbol:
Address:
Symbol:
Address:
R/W
R/W
R/W
0
2
2
0
2
0
R/W
R/W
R/W
PST4
6Ah
PST5
6Bh
LPFBDC
71h
1
0
1
0
1
1
CH7304
LPFBD0
TPOFF0
R/W
R/W
R/W
0
0
0
1
0
1
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