ch7304 Chrontel, ch7304 Datasheet - Page 13

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
3.0 Register Control
The CH7304 is controlled via a serial port. The serial bus uses only the SC clock to latch data into registers, and does
not use any internally generated clocks so that the device can be written to in all power down modes. The device should
retain all register values during power down modes. For registers read/write operation, please refer to applications note
AN-61 for details.
3.1
The register controls are listed below, divided into three sections: General & Power Down controls, Input/Output
controls, and LVDS controls.
GENERAL & POWER DOWN CONTROLS
CLKDETD
DID[7:0]
LODPDB[1:0]
LVDSPD
PANEN
RESETIB
RESETDB
TPBLD [6:0]
TPBLE [6:0]
TPOFF [8:0]
TPON [8:0]
TPPWD [5:0]
TSTP[1:0]
VID[7:0]
INPUT/OUTPUT CONTROLS
IBS
IDF[2:0]
MCP
RGB
XCM
XCMD[3:0]
LVDS CONTROLS
BGLMT[7:0]
BKLEN
FRSTB
LDD
LDI
LDEN[1:0]
LEOSWP
LODA[2:0]
LODP
LODPE
LODST
LPCP[2:0]
LPFBD[3:0]
LPFFD[1:0]
LPFORC
LPLEN
201-0000-053
Control Registers Index
Rev. 1.31, 6/14/2006
Input buffer type select
Input Data Format
XCLK Polarity Control
YCrCb to RGB
XCLK 1X / 2X select
Delay adjust between XCLK and D[11:0]
XCLK Detection Defeat
Device ID register
LVDS Power Down
Panel Enable (0 – begin Power off sequence, 1 Power-on)
Software SPP (serial port) reset
Timer – Black Light Enable (T2)
Timer - Power On (T1)
Timer – Power Cycle (T5)
Enable/select test pattern generation (color bar, ramp)
Version ID register
LVDS Output Driver Power Down control
Software datapath reset
Timer – Black Light Disable (T3)
Timer – Power Off (T4)
Bang Limit control of internal LVDS FIFO over/under run
Backlight enable
FIFO Reset Enable
LVDS Dithering Defeat
Open LDI mode
LVDS Output Driver enable
Odd/even sample output swap on LVDS link
LVDS Output Driver Amplitude control for bank 1
LVDS Output Driver Pull-down
LVDS Output Driver Pre-emphasis
LVDS Output Driver Source Termination control
LVDS PLL Charge pump control
LVDS PLL feed back divider controls
LVDS PLL feed forward divider controls
Bypass LVDS PLL Lock Detect Sentry
Enable Bypass of LVDS PLL Lock Detect
Address
14h
4Bh
76h
63h
66h
48h
48h
69h
68h
69h-6Ah
67h-68h
6Bh
48h
4Ah
Address
1Fh
1Fh
1Ch
31h
1Ch
1Dh
Address
7Fh
66h
76h
64h
64h
73h
64h
74h
74h
74h
75h
73h
71h
71h
66h
66h
CH7304
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