UPD70208HGF-12-3B9 NEC [NEC], UPD70208HGF-12-3B9 Datasheet - Page 79

• Manufacturer Part Number: UPD70208HGF-12-3B9
• Description: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
• Manufacturer: NEC [NEC]

(1)
TOUT1
TCTL2 setup time (vs. CLKOUT )
TCTL2 setup time (vs. TCLK )
TCTL2 hold time (vs. CLKOUT )
TCTL2 hold time (vs. TCLK )
TCTL2 high-level width
TCTL2 low-level width
TOUT output delay time (vs. CLKOUT )
TOUT output delay time (vs. TCLK )
TOUT output delay time (vs. TCTL2 )
TCLK rise time
TCLK fall time
TCLK high-level width
TCLK low-level width
TCLK cycle
Access interval
REFRQ delay time (vs. MRD )
RESET pulse width
Notes 1. Specification to guarantee read/write recovery time for I/O device.
PD70208H, 70216H-10/12/16 (T
2. Specification to guarantee that REFRQ is always later than MRD .
3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation
T
X
Only guaranteed when the EREF bit of the SCTL register is 0.
stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending
on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the
resonator and oscillator actually used.
D delay time
Note 1
Note 3
Parameter
Note 2
A
= –40 to +85 C, V
Data Sheet U13225EJ4V0DS00
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Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DTX
SGK
SGTK
HKG
HTKG
GGH
GGL
DKTO
DTKTO
DGTO
TKR
TKF
TKTKH
TKTKL
CYTK
AI
DRQHRH
WRESL
DD
= 3 V 10%) (3/3)
2t
t
MIN.
KKL
PD70208H-10
PD70216H-10
4t
CYK
100
200
50
50
50
50
50
60
60
CYK
–50
–70
MAX.
500
200
150
120
DC
25
25
2t
t
KKL
MIN.
PD70208H-12
PD70216H-12
CYK
4t
Output Pin Load Capacitance: C
100
166
50
50
50
50
50
55
55
CYK
–40
–60
PD70208H, 70216H
MAX.
500
200
150
120
DC
25
25
2t
t
KKL
CYK
4t
MIN.
PD70208H-16
PD70216H-16
100
125
50
50
50
50
50
50
50
CYK
–30
–50
MAX.
500
200
150
120
DC
25
25
L
= 100 pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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