UPD70208HGF-12-3B9 NEC [NEC], UPD70208HGF-12-3B9 Datasheet - Page 39
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UPD70208HGF-12-3B9
Manufacturer Part Number
UPD70208HGF-12-3B9
Description
V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
Manufacturer
NEC [NEC]
Datasheet
1.UPD70208HGF-12-3B9.pdf
(110 pages)
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following conditions.
(1) V40HL
The instruction set is shown in tabular form on the following pages.
Clock cycle shown in table is the time required for execution of instruction by the execution unit and is based on the
The number of clock cycle of instruction with byte processing and word processing (with W bit) is shown as the followings.
For the clock of block transfer related instruction of V40HL, see Table 15-8.
On the left of "/"
On the right of "/": The value corresponding to word processing (W =1) of odd address
• Prefetch time and wait time for using bus, etc. are not included.
• 0 wait is assumed for memory access. That is, the clock number of one bus cycle is four clock cycle.
• 0 wait is assumed for I/O access.
• Primitive block transfer instruction and primitive input/output instruction is included repeat prefixes.
Remark
Table 15-8. Number of Clock Cycles in Block Transfer Related Instruction (V40HL)
MOVBK
CMPBK
CMPM
LDM
STM
INM
OUTM
Instruction
The figures in parentheses apply to one-time processing only.
:
The value corresponding to byte processing (W= 0) or word processing (W = 1) of even
address
Byte Processing (W = 0)
7 + 14
7 + 10
9 + 8
7 + 9
5 + 4
9 + 8
9 + 8
Data Sheet U13225EJ4V0DS00
(13)
(10)
(10)
(9)
(7)
(7)
(5)
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Number of Clock Cycles
Word Processing (W = 1)
9 + 16
7 + 22
7 + 14
7 + 13
9 + 16
9 + 16
5 + 8
(17)
(21)
(11)
(11)
(18)
(18)
(9)
PD70208H, 70216H
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39
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