UPD70208HGF-12-3B9 NEC [NEC], UPD70208HGF-12-3B9 Datasheet - Page 24
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UPD70208HGF-12-3B9
Manufacturer Part Number
UPD70208HGF-12-3B9
Description
V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
Manufacturer
NEC [NEC]
Datasheet
1.UPD70208HGF-12-3B9.pdf
(110 pages)
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24
4. CG (CLOCK GENERATOR)
and X2 pins, supplies it as the CPU operating clock and outputs it externally as the CLKOUT pin output.
system I/O area register.
5. BIU (BUS INTERFACE UNIT)
unit) and REFU (refresh control unit).
generator (CG). In addition to being supplied to the inside of the V40HL and V50HL, the synchronized reset signal is also
output externally from the RESOUT pin. The synchronized READY signal is supplied to the internal CPU, DMAU and REFU.
The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1
The interrupt cycle time can be changed according to the oscillator scaling factor. The scaling factor can be set by a
The BIU controls the data bus, address bus and control bus pins. These buses are used by the CPU, DMAU (DMA control
The BIU synchronizes the RESET input signal and READY input signal using the CLOCK signal generated by the clock
X1
X2
RESET
READY
Oscillator
Figure 5-1. RESET and READY Signal Synchronization
CLOCK
f
XX
D
Figure 4-1. Internal Block Diagram of CG
Divide-by-2
Scaler
CK
Data Sheet U13225EJ4V0DS00
Q
Divide-by-1-to-8
Scaler
Divide-by-2-to-16
Scaler
D
D
CK
CK
Q
Q
f
X
PD70208H, 70216H
CPU, DMAU, REFU, SCU
CLKOUT
Baud Rate Counter (BRC)
TCU
To Internal Units
To Internal Units
RESOUT
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