ch7019 Chrontel, ch7019 Datasheet - Page 66

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
LPPDN (bit 3) of register LPDLFR controls the LVDS PLL Power Down.
LPLF[2:0] (bits 6-4) of register LPDLFR control the LVDS PLL Loop Filter Resistor per the following table:
FRSTB (bit 7) of register LPDLFR controls the FIFO reset.
LVDS Control 2
LPPD[4:0] (bits 4-0) of register LVCTL2 define the LVDS PLL Phase Detector Control. The recommended values are
shown in Table 39 in section 3.4.
LPLF[4:3] (bits 6-5) of register LVCTL2 control the LVDS PLL Loop Filter Capacitor. The recommended settings are
shown in Table 39.
This register limits the allowable occurrences of internal LVDS FIFO over and under-runs within one VGA frame.
66
Bang Limit Control
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
LPPDN
FRSTB
TYPE:
TYPE:
BIT:
BIT:
Table 38: LVDS PLL Loop Filter Resistor
BGLMT7 BGLMT6 BGLMT5 BGLMT4 BGLMT3 BGLMT2 BGLMT1 BGLMT0
Reserved
LPLF2
= 0 =>
= 1 =>
= 0 =>
= 1 =>
R/W
R/W
0
0
0
0
0
0
1
1
1
1
7
7
LVDS PLL is powered down
Normal operation
Enable FIFO Reset
Normal Operation
LPLF1
LPLF4
R/W
R/W
6
0
6
0
0
0
1
1
0
0
1
1
LPLF0
LPLF3
R/W
R/W
5
1
5
0
0
1
0
1
0
1
0
1
PLL Loop Filter Resistor Value (Ohm)
LPPD4
R/W
R/W
4
1
4
1
LPPD3
R/W
R/W
3
1
3
0
21,800
42,600
11,000
73,200
1800
2600
1000
3200
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
201-0000-048
LPPD2
R/W
R/W
2
0
2
0
LPPD1
R/W
R/W
LVCTL2
78h
7
BGLMT
7Fh
8
Rev. 2.4, 12/18/2006
1
0
1
0
CH7019B
LPPD0
R/W
R/W
0
0
0
0