ch7019 Chrontel, ch7019 Datasheet - Page 6

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Table 1: Pin Description (continued)
6
Pin #
53
59
61
76, 74
85-90, 94-99
93, 91
64, 83, 84, 103 4
67, 75, 92, 100 4
60
55
54
51
37
39, 48
7, 13, 19, 20,
26, 32
4, 10, 16, 23,
29, 35
1
3
8, 9, 21, 22,
109, 110, 112-
122
68-73, 77-82
# of Pins Type
1
1
1
12
2
12
2
1
1
1
1
1
1
6
6
1
1
17
Out
Out
In
In
In
In
In
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Symbol
XO
P-Out
VREF1
D1[11:0]
XCLK1,
XCLK1*
D2[11:0]
XCLK2,
XCLK2*
DVDD
DGND
VDDV
TVPLL_VDD
TVPLL_VCC
TVPLL_GND
DAC_VDD
DAC_GND
LVDD
LGND
LPLL_VDD
LPLL_GND
N/C
Description
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XI / FIN. However, if an external CMOS clock is
attached to XI/FIN, XO should be left open.
Pixel Clock Output
This pin provides a pixel clock signal to the VGA controller which can be
used as a reference frequency. The output is selectable between 1X and
2X of the pixel clock frequency.
VDDV supply (pin 60). This output has a programmable tri-state. The
capacitive loading on this pin should be kept to a minimum.
Reference Voltage Input 1
The VREF1 pin inputs a reference voltage of VDDV / 2.
derived externally through a resistor divider and decoupling capacitor, and
will be used as a reference level for data, sync and clock inputs.
Data1[11] through Data1[0] Inputs
These pins accept the 12 data inputs from a digital video port of a graphics
controller. The levels are 0 to VDDV. VREF1 is the threshold level.
External Clock Inputs
These inputs form a differential clock signal input to the device for use
with the H1, V1 and D1[11:0] data.
available, the XCLK1* input should be connected to VREF1. The clock
polarity can be selected by the MCP1 control bit.
Data2[11] through Data2[0] Inputs
These pins accept the 12 data inputs from a digital video port of a graphics
controller. The levels are 0 to VDDV. VREF1 is the threshold level.
External Clock Inputs
These inputs form a differential clock signal input to the device for use
with the H2, V2 and D2[11:0] data.
available, the XCLK2* input should be connected to VREF1. The clock
polarity can be selected by the MCP2 control bit.
Digital Supply Voltage (3.3V)
Digital Ground
I/O Supply Voltage (1.1V to 3.3V)
TV PLL Supply Voltage (3.3V)
TV PLL Supply Voltage (3.3V)
TV PLL Ground
DAC Supply Voltage (3.3V)
DAC Ground
LVDS Supply Voltage (3.3V)
LVDS Ground
LVDS PLL Supply Voltage (3.3V)
LVDS PLL Ground
Not Connected
201-0000-048
The output driver is driven from the
If differential clocks are not
If differential clocks are not
Rev. 2.4, 12/18/2006
CH7019B
The signal is