ch7019 Chrontel, ch7019 Datasheet - Page 59

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
LCNTLF and LCNTLE (bits 1-0) of register LVDSE2 are OpenLDI miscellaneous control signals, Cntl F and Cntl E,
for the Display Source Serializer respectively. Refer to the OpenLDI specification v0.95. See section 2.4.2.
LA6RL (bit 3) of register LVDSE2 is an OpenLDI reserved bit for future use and may take any value. Refer to the
OpenLDI specification v0.95, P5. See section 2.4.2.
C5GP[5:3] (bits 7-5) of register LVDSE2 define the GPIO C5 Control bits [5:3]. The entire bit field is made up of these
bits C5GP[5:3] plus C5GP[2:0] contained in the GPIO Invert register (5Ch, bits 7-5). C5GP[5:0] invert the data output
on the GPIO[5:0] pins when the pins are configured in output mode. When the corresponding GOENB bits
(GOENB[5:0], see GPIODC register, address 6Eh, bits 3-0 and GPIO register, address 1Eh, bits 7-6) are ‘0’ and the
corresponding C5GP bits are ‘1’ the values in GPIOL[5:0] are driven out inverted at the corresponding GPIO pins.
LVDS PLL Miscellaneous Control Register
The LMPC register controls panel protection circuits which control the LVDS panel power up and down sequence. Refer
to section 3.4.5 and to Figure 19.
PANEN (bit 0) of the LPMC register controls the LVDS panel enable.
LSYNCEN (bit 1) of the LMPC register controls the Sync Detection Bypass
LPLOCK (bit 2) of the LMPC register indicates the status of the PLL Lock
LPFORC (bit 3) of the LMPC register : Bypass LVDS Lock Detect Sentry
LPLEN (bit 4) of the LMPC register controls LVDS PLL Lock Enable between LPLOCK and LPFORC.
BKLEN (bit 5) of the LMPC register enables the panel backlight.
SYNCST(bit 6) of the LMPC register is the Hsync and Vsync stability status bit. Refer to section 3.4.5.
Note: The order of programming the control registers for the power up sequence is very important. Both
LPLOCK and SYNCST must read as 1 before setting PANEN to 1. Doing so will eliminate unexpected results on
the LCD panel.
201-0000-048
DEFAULT:
SYMBOL:
PANEN
LSYNCEN = 0 => Normal Operation. HSYNC and VSYNC detection enabled.
LPLOCK
Bit 3
LPLEN
BKLEN
SYNCST
TYPE:
BIT:
Reserved
= 0 => Begin Power off sequence
= 1 => Power-on
= 1 => HSYNC and VSYNC detection circuit is bypassed enabling forced power up sequence.
= 0 => PLL is not stable.
= 1 => PLL is stable and properly locked.
= 0 => Lock detect sentry is active.
= 1 => Lock detect sentry is overridden if LPLEN is set to ‘1’.
= 0 => Select LPLOCK (normal operation)
= 1 => Select LPFORC (Lock detect sentry is overridden if LPFORC is set to ‘1’)
= 0 => Disable Backlight
=1 => Enable Backlight
= 0 => Hsync or Vsync are not stable
= 1 => Hsync and Vsync are stable
R/W
Rev. 2.4,
0
7
SYNCST
12/18/2006
R
6
0
BKLEN
R/W
3
0
LPLEN LPFORC LPLOCK LSYNCEN PANEN
R/W
4
0
R/W
3
0
Symbol:
Address:
Bits:
R
2
0
LPMC
66h
7
R/W
1
0
CH7019B
R/W
0
1
59