ch7019 Chrontel, ch7019 Datasheet - Page 40

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
CVBW (bit 5) of register VBW controls the chroma component of the CVBS signal. CVBW = ‘0’ disables the chroma
signal being added to the CVBS signal, CVBW = ‘1’ enables the chroma signal being added to the CVBS signal.
CFRB (bit 6) of register VBW controls whether the chroma sub-carrier free-runs, or is locked to the video signal. A ‘1’
causes the sub-carrier to lock to the TV vertical rate, and should be used when the CIVEN bit (register 10h) is set to ‘0’.
A ‘0’ causes the sub-carrier to free-run, and should be used when the CIVEN bit is set to ‘1’.
VBID (bit 7) of register VBW controls the vertical blanking interval defeat function. A ‘1’ in this register location
forces the flicker filter to minimum filtering during the vertical blanking interval. A ‘0’ in this location causes the flicker
filter to remain at the same setting inside and outside of the vertical blanking interval.
Text Enhancement Register
TE[2:0] (bits 2-0) of register TE control the text enhancement circuitry within the CH7019. A value of ‘000’ minimizes
the enhancement feature, while a value of ‘111’ maximizes the enhancement.
SAV8, HP8 and VP8 (bits 5-3) of register TE contain the MSB values for the start of active video, horizontal position
and vertical position controls. They are described in detail in the SAV (address 04h), HP (address 05h) and VP (address
06h) register descriptions.
PTSEL[1:0] (bits 7-6) of register TE control the data path from D1[11:0] and D2[11:0] inputs to internal TV and LVDS
blocks. These bits allow one to swap the input data paths to internal TV or LVDS blocks. The default setting which
routes D1 input to TV block and D2 input to LVDS block is recommended.
Start of Active Video Register
40
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
PTSEL1
PTSEL1
SAV7
R/W
R/W
7
1
7
0
0
0
1
1
PTSEL0
PTSEL0
SAV6
R/W
R/W
6
0
6
1
1
0
0
1
D1 input is routed to both internal TV and LVDS block
D1 input is routed to LVDS and D2 input is routed to TV block
D1 input is routed to TV and D2 input is routed to LVDS block
D2 input is routed to both internal TV and LVDS block
Description
SAV8
SAV5
R/W
R/W
5
0
5
0
SAV4
R/W
R/W
HP8
4
0
4
1
SAV3
R/W
R/W
VP8
3
0
3
0
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
201-0000-048
SAV2
R/W
R/W
TE2
2
1
2
0
SAV1
R/W
R/W
TE1
TE
03h
8
SAV
04h
8
Rev. 2.4, 12/18/2006
1
0
1
0
CH7019B
SAV0
R/W
R/W
TE0
0
1
0
0