SI3452 SILABS [Silicon Laboratories], SI3452 Datasheet - Page 32
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SI3452
Manufacturer Part Number
SI3452
Description
QUAD HIGH-VOLTAGE PORT CONTROLLER FOR POE AND POE+ PSES
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
1.SI3452.pdf
(36 pages)
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Si3452/3
32
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4x4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
be used to assure good solder paste release.
center Vee pad.
specification for Small Body Components.
Dimension
Table 27. PCB Land Pattern Dimensions (Continued)
GE
GD
D2
ZE
ZD
E2
D
X
Y
Rev. 1.0
4.00
4.00
4.53
4.53
Min
—
—
—
5.42 REF
0.89 REF
Max
4.20
4.20
0.28
6.31
6.31
—
—