SI3201-X-FS SILABS [Silicon Laboratories], SI3201-X-FS Datasheet - Page 89

• Manufacturer Part Number: SI3201-X-FS
• Manufacturer: SILABS [Silicon Laboratories]

4.4. FK Control
For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These
registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,
bit 6) and REL = 1 (direct Register 32, bit 6).
Addr D15
69
70
71
72
73
74
Addr
20
21
22
23
24
25
26
27
64
66
Power Alarm Threshold for Transistors Q3 and Q4.
Power Alarm Threshold for Transistors Q5 and Q6.
Loop Closure Filter Coefficient.
Ring Trip Filter Coefficient.
Thermal Low Pass Filter Pole for Transistors Q1 and Q2.
Thermal Low Pass Filter Pole for Transistors Q3 and Q4.
Thermal Low Pass Filter Pole for Transistors Q5 and Q6.
Common Mode Bias Adjust During Ringing.
Recommended value of 0 decimal.
DC-DC Converter V
This register sets the overhead voltage, V
bit = 0 (direct Register 66, bit 4), V
VOV bit = 1, V
Loop Closure Threshold—Lower Bound.
This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of
direct Register 108. The range is 0–80 mA in 1.27 mA steps.
D14
Table 36. SLIC Control Indirect Registers Description (Continued)
D13
Table 37. FSK Control Indirect Registers Summary
OV
D12
should be set between 0 and 13.5 V (VMIND = 0 to 9h).
OV
D11
Voltage (Si3233 only).
D10
Preliminary Rev. 0.5
OV
D9
should be set between 0 and 9 V (VMIND = 0 to 6h). When the
FSK0X[15:0]
FSK1X[15:0]
FSK01[15:0]
FSK10[15:0]
FSK0[15:0]
FSK1[15:0]
OV
D8
Description
, to be supplied by the dc-dc converter. When the VOV
D7
D6
D5
D4
D3
D2
Si3233
D1
D0
89