SI3201-X-FS SILABS [Silicon Laboratories], SI3201-X-FS Datasheet - Page 22

• Manufacturer Part Number: SI3201-X-FS
• Manufacturer: SILABS [Silicon Laboratories]

Si3233
2.2.6. Loop Closure Detection
A loop closure event signals that the terminal equipment
has gone off-hook during on-hook transmission or on-
hook active states. The ProSLIC performs loop closure
detection digitally using its on-chip monitor A/D
converter. The functional blocks required to implement
loop closure detection are shown in Figure 9. The
primary input to the system is the Loop Current Sense
value provided in the LCS register (direct Register 79).
The LCS value is processed in the Input Signal
Processor when the ProSLIC is in the on-hook
transmission or on-hook active linefeed state, as
indicated by the Linefeed Shadow register, LFS[2:0]
(direct Register 64). The data then feeds into a
programmable digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
The output of the low-pass filter is compared to a
programmable threshold, LCRT (indirect register 15).
The threshold comparator output feeds a programmable
22
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
Power Alarm Interrupt Enable
LCS
LVS
Automatic/Manual Detect
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Table 22. Associated Power Monitoring and Power Fault Registers (Continued)
Processor
Power Alarm
LFS
Signal
Input
LCVE
ISP_OUT
HYSTEN
Digital
NCLR
LPF
Figure 9. Loop Closure Detection
1 = enter open state
spond to Q1 to Q6,
upon power alarm
0 = manual mode
Bits 2 to 7 corre-
respectively
Loop Closure
LCRT
Threshold
Preliminary Rev. 0.5
LCRTL
+
–
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the loop closure debounce interval,
LCDI (direct Register 69). If the debounce interval has
been satisfied, the LCR bit will be set to indicate that a
valid loop closure has occurred. A loop closure interrupt
is generated if enabled by the LCIE bit (direct
Register 22). Table 23 lists the registers that must be
written or monitored to correctly detect a loop closure
condition.
2.2.7. Loop Closure Threshold Hysteresis
Programmable hysteresis to the loop closure threshold
can be enabled by setting HYSTEN = 1 (direct
Register 108, bit 0). The hysteresis is defined by LCRT
(indirect Register 15) and LCRTL (indirect Register 66),
which set the upper and lower bounds, respectively.
N/A
N/A
Debounce
Filter
LCDI
where n = 1 to 6
QnAE[n+1],
AOPN
LCR
Interrupt
Logic
Direct Register 22
Direct Register 67
LCIE
LCIP