vpx3224d ETC-unknow, vpx3224d Datasheet - Page 38

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

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VPX 3225D, VPX 3224D
2.16. JTAG Boundary-Scan, Test Access Port (TAP)
The design of the Test Access Port, which is used for
Boundary-Scan Test, conforms to standard IEEE
1149.1-1990, with one exception. Also included is a list
of the mandatory instructions supported, as well as the
optional instructions. The following comprises a brief
overview of some of the basics, as well as any optional
features which are incorporated. The IEEE 1149.1 docu-
ment may be necessary for a more concise description.
Finally, an adherence section goes through a checklist
of topics and describes how the design conforms to the
standard.
The implementation of the instructions HIGHZ and
CLAMP conforms to the supplement P1149.1/D11 (Oc-
tober 1992) to the standard 1149.1-1990.
2.16.1. General Description
The TAP in the VPX is incorporated using the four signal
interface. The interface includes TCK, TMS, TDI, and
TDO. The optional TRESET signal is not used. This is
not needed because the chip has an internal power-on-
reset which will automatically steer the chip into the
TEST-LOGIC-RESET state. The goal of the interface is
to provide a means to test the boundary of the chip.
There is no support for internal or BIST(built-in self test).
The one exception to IEEE 1149.1 is that the TDO output
is shared with the LLC2 signal. This was necessitated
due to I/O restrictions on the chip (see section 2.16.3.
“Exceptions to IEEE 1149.1” for more information).
2.16.2. TAP Architecture
The TAP function consists of the following blocks: TAP-
controller, instruction register, boundary-scan register,
bypass register, optional device identification register,
and master mode register.
2.16.2.1. TAP Controller
The TAP controller is responsible for responding to the
TCK and TMS signals. It controls the transition between
states of this device. These states control selection of
the data or instruction registers, and the actions which
occur in these registers. These include capture, shifting,
and update. See Fig. 5–1 of IEEE 1149.1 for TAP state
diagram.
2.16.2.2. Instruction Register
The instruction register chooses which one of the data
registers is placed between the TDI and TDO pins when
the select data register state is entered in the TAP con-
troller. When the select instruction register state is ac-
tive, the instruction register is placed between the TDI
and TDO.
Instructions
The following instructions are incorporated:
– bypass
– sample/preload
– extest
– master mode
– ID code
– HIGHZ
– CLAMP
2.16.2.3. Boundary Scan Register
The boundary scan register (BSR) consists of boundary
scan cells (BSCs) which are distributed throughout the
chip. These cells are located at or near the I/O pad. It al-
lows sampling of inputs, controlling of outputs, and shift-
ing between each cell in a serial fashion to form the BSR.
This register is used to verify board interconnect.
Input Cell
The input cell is constructed to achieve capture only.
This is the minimal cell necessary since Internal Test
(INTEST) is not supported. The cell captures either the
system input in the CAPTURE-DR state or the previous
cells output in the SHIFT-DR state. The captured data is
then available to the next cell. No action is taken in the
UPDATE-DR state. See Figure 10–11 of IEEE 1149.1 for
reference.
Output Cell
The output cell will allow both capture and update. The
capture flop will obtain system information in the CAP-
TURE-DR state or previous cells information in the
SHIFT-DR state. The captured data is available to the
next cell. The captured or shifted data is downloaded to
the update flop during the UPDATE-DR state. The data
from the update flop is then multiplexed to the system
output pin when the EXTEST instruction is active. Other-
wise, the normal system path exists where the signal
from the system logic flows to the system output pin. See
Fig. 10–12 of IEEE 1149.1 for reference.
PRELIMINARY DATA SHEET
Micronas