vpx3224d ETC-unknow, vpx3224d Datasheet - Page 36

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

36
VPX 3225D, VPX 3224D
Write to Hardware Control Registers
Read from Hardware Control Registers
Note:
SDA
SCL
Fig. 2–40: I
2.14.5. FP Control and Status Registers
Due to the internal architecture of the VPX, the IC cannot
react immediately to all I
the embedded processor (FP). The maximum response
timing is appr. 20 ms (one TV field) for the FP processor
if TV standard switching is active. If the addressed pro-
cessor is not ready for further transmissions on the I
bus, the clock line SCL is pulled low. This puts the cur-
Write to FP
Read from FP
S
S
S
S
S
S
1 0 0 0 0 1 1 0
1 0 0 0 0 1 1 0
1 0 0 0 0 1 1 0
1 0 0 0 0 1 1 0
1 0 0 0 0 1 1 0
2
S =
P =
ACK = Acknowledge-Bit (active low on SDA from receiving device)
NAK = No Acknowledge-Bit (inactive high on SDA from receiving device)
C bus protocol
S
1 0 0 0 0 1 1 0
ACK
ACK
ACK
ACK
I
I
2
2
C-Bus Start Condition
C-Bus Stop Condition
2
C requests which interact with
ACK
FPDAT
FPDAT
FPWR
FPRD
(MSB first)
ACK
sub-addr
ACK
ACK
ACK
ACK
1
0
send FP-address-
send FP-address-
send data-byte
S
byte high
byte high
high
ACK
2
sub-addr
1 0 0 0 0 1 1 1
C
S
ACK
ACK
ACK
rent transmission into a wait state called clock synchro-
nization. After a certain period of time, the VPX releases
the clock and the interrupted transmission is carried on.
Before accessing the address or data registers for the
FP interface (FPRD, FPWR, FPDAT), make sure that
the busy bit of FP is cleared (FPSTA).
1 0 0 0 0 1 1 1
ACK
send FP-address-
send FP-address-
send data-byte
byte low
byte low
low
ACK
receive data-byte
high
P
ACK
ACK
ACK
ACK
send data-byte
PRELIMINARY DATA SHEET
ACK
P
P
P
receive data-byte
receive data-byte
low
NAK
ACK
NAK
Micronas
P
P
P