vpx3224d ETC-unknow, vpx3224d Datasheet - Page 20

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

20
VPX 3225D, VPX 3224D
2.6.1.3. Embedded Timing Codes (BStream)
In this mode, several event words are inserted into the
pixel stream for timing information. It is activated by set-
ting Bit[1:0] of FP-RAM 0x150 to 10. Each event word
consists of a chrominance code value containing the
phase of the color-multiplex followed by a luminance
code value signalling a specific event. The allowed con-
trol codes are listed in table 2–6 and 2–7.
At the beginning and the end of each active video line,
timing reference codes (start of active video: SAV; end
of active video: EAV) are inserted with the beginning and
the end of VACT. Since VACT is suppressed during
blanked lines, video data and SAV/EAV codes are pres-
ent during active lines only. If raw/sliced data should be
output, VACT has to be enabled during the VBI window
with bit 2 of FP-RAM 0x138! In the case of several win-
dows per field, the length of the active data stream per
line can vary. Since the qualifiers for active video (SAV/
EAV) are independent of the other reference codes,
there is no influence on horizontal or vertical syncs, and
sync generation can be performed even with several dif-
ferent windows. For full compliance with applications re-
quiring data streams of a constant size, the VPX pro-
vides a mode with programmable ‘video active’ signal
VACT which can be selected via bit 2 of FP-RAM 0x140.
The start and end positions of VACT relative to HREF is
determined by FP-RAM 0x151 and 0x152. The delay of
valid data relative to the leading edge of HREF is calcu-
lated with the formulas given in table 2–8 and 2–9. The
result can be read in FP-RAM 0x10f (for window 1) and
0x11f (for window 2). Be aware that the largest window
defines the size of the needed memory. In the case of
1140 raw VBI-samples and only 32 scaled video sam-
ples, the graphics controller needs 570 words for each
line (the VBI-samples are multiplexed to luminance and
chrominance paths).
The leading edge of HREF indicates the beginning of a
new video line. Depending on the type of the current line
(active or blanked), the corresponding horizontal refer-
ence code is inserted. For big window sizes, the leading
edge of HREF can arrive before the end of the active
data. In this case, hardware assures that the control
code for HREF is delayed and inserted after EAV only.
The VREF control code is inserted at the falling edge of
VREF. The state of HREF at this moment indicates the
current field type (HREF = 0: odd field; HREF = 1: even
field).
In this mode, the words 0,1,254, and 255 are reserved
for data identifications. This is assured by limitation of
the video data.
video data
FP-RAM 0x154 [outmux]
Table 2–6: Chrominance control codes
2.6.2. Bus Shuffler
In the YUV 4:2:2 mode, the output of luminance data is
on port A and chrominance data on Port B. With the bus
shuffler, luminance can be switched to Port B and chro-
minance to port A. In 8-bit double clock mode, shuffling
can be used to swap the Y and C components. It is se-
lected with FP-RAM 0x150.
2.6.3. Output Multiplexer
During normal operation, a 16-bit YUV 4:2:2 data stream
is transferred synchronous to an internally generated
PIXCLK at a rate of 13.5 MHz. Data can be latched onto
the falling edge of PIXCLK or onto the rising edge of LLC
during high PIXCLK. In the double clock mode, lumi-
nance and chrominance data are multiplexed to 8 bit and
transferred at the double clock frequency of 27 MHz in
the order Cb, Y, Cr, Y...; the first valid chrominance value
being a Cb sample. With shuffling switched on, Y and C
components are swapped. Data can be latched with the
rising edge of LLC or alternating edges of PIXCLK. This
mode is selected with bit 9 of FP-RAM 0x154. All 8-bit
modes use Port A only. In this case, Port B can be acti-
vated as programmable output with bit 8 of FP-RAM
0x154. Bit 0–7 determine the state of Port B.
Fig. 2–21: Programmable output port
2.6.4. Output Ports
The two 8-bit ports produce TTL level signals coded in
binary offset. The Ports can be tristated either via the
output enable pin (OE) or via I
information, see section 2.17. “Enable/Disable of Output
Signals”.
Chroma Value
FE
FF
8
8
7:0
=0
=1
PRELIMINARY DATA SHEET
8
2
C register 0xF2. For more
Phase Information
Cr pixel
Cb pixel
8
B[7:0]
video port
Micronas