vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 13

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
2.3
2.4
Table 1. CKSEL Settings
I/O Logic
Each general-purpose 5-V tolerant I/O pin is controlled by a set of registers in the Control register block.
The I/O supports a high current drive output buffer that can be configured as a totem pole or open-drain
driver. The input section of the I/O supports TTL signaling and includes an internal weak pull-up device.
This allows unused I/O pins to be left unconnected without high-current drain issues. The port bypass
control I/O pins, which are shared with Port 3, Port 4, Port 5, and Port 6, are generated using the same
buffer logic as the other ports. When enabled in Port Bypass Control mode, internal logic overrides the
existing configuration, with each I/O pin dedicated to the specific port bypass function. All I/O lines
default as inputs with the weak internal pull-up enabled.
Clock Generator
Clock generation for the device is composed of an internal oscillator, divider circuits, and a distribution
network. It supports nominal clock frequencies of:
The three CKSEL inputs select one of the eight available fixed clock frequencies, as well as determining
the frequency of the CKOUT output. The internal low-frequency clock (8.0 MHz to 12.5 MHz) is used for
filtering incoming serial interface signals and interrupt sources, as well as for clocking the slave state
machine. Divided clocks provide the source for LED flash rate generators. The oscillator provides a stable
clock source for the device and requires the use of an off-chip crystal with a frequency of 8.0 MHz,
8.33 MHz, 8.854 MHz, or 10.0 MHz and related passive components or external clock source. The
available fixed clock rates have been selected to allow the use of other system clocks which may be
available as well as low-cost crystals. Additionally, when using a high frequency clock, the CKOUT pin
provides a divided clock that can be used to drive other VSC055-01 devices within the system. This
mechanism ensures that a single additional load is placed on the system clock with all subsequent clock
inputs daisy-chained from the first VSC055-01.
The following table describes the CKSEL settings for the available fixed input clocks and the associated
divider value and CKOUT frequency.
●
●
●
●
●
●
●
●
CKSEL2
8.0 MHz
8.33 MHz
8.854 MHz
10.0 MHz
33.33 MHz
40.0 MHz
50.0 MHz
53.125 MHz
VDD
VSS
VSS
VSS
VSS
CKSEL1
VSS
VSS
VDD
VDD
VSS
CKSEL0
VDD
VDD
VSS
VSS
VSS
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Input Clock
8.854 MHz
10.0 MHz
8.33 MHz
40.0 MHz
8.0 MHz
Divider
N/A
N/A
N/A
N/A
÷4
Internal Clock
8.854 MHz
10.0 MHz
8.33 MHz
10.0 MHz
8.0 MHz
January 2008
Revision 4.1