vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 113

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
3.2.100 FEh: Clock Divider Control (CDC)
Table 9. Clock Divider
The following table shows the bit assignments for the Clock Divider Control register.
The following table lists the appropriate CKSEL input clock divider values for the ICD bit.
Register Name:
Address:
Reset Value:
Bit
7:0
CKSEL2
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
Bit Label
ICD
CKSEL1
VSS
VSS
VSS
VSS
NA
NA
NA
NA
NA
CDC
FEh
0000_0000b
Access
R/W
CKSEL0
NA
NA
NA
NA
NA
NA
NA
NA
NA
Description
Internal Clock Divider
These bits enable an internal clock divider that adjusts the clock source for the
fan speed control and LED blink control logic to provide a 20 kHz base
frequency.
Under normal conditions, when these bits remain reset, the CKSEL inputs
determine the divide-by value used for generation of the 20 kHz base
frequency. If an external clock source between 8.0 MHz and 12.5 MHz or
32.0 MHz and 75.0 MHz that is not equal to one of the available frequencies
defined by the CKSEL inputs is desired, this register should be programmed
appropriately to adjust the divider.
To simplify programming and provide an 8-bit value that can cover the desired
range, the input clock source is divided by 3. This divider is positioned after the
primary high-frequency divider, therefore proper connection of the CKSEL2
and CKSEL1 inputs is required to determine if both the source is a
high-frequency source and whether it should be divided by 4 or divided by 6.
For example, if 66.67 MHz is the input clock frequency, the CKSEL2 and
CKSEL1 inputs would be connected to V
11.11 MHz internal clock, which is within the 8.0 MHz to 12.5 MHz operating
range of the VSC055-01. The 11.11 MHz internal clock is then divided by 3
(3.7 MHz) and then divided by 185 (B8h is loaded into the CDC register) to
achieve 20.02 kHz.
To enable the divider, set bit 7 of this register to a 1. This limits the available
divide by values from 129 (80h) to 256 (FFh), with a useful range of 133 (84h)
to 208 (CFh).
divider values required to achieve the desired results with several input clock
frequencies that are not available as part of the fixed divider logic. The CKSEL
inputs must always be connected to either V
input clock range but in some cases, the value on CKSEL1 and CKSEL0 may
not be important when using the CDC register.
After a reset or power on, these register bits are cleared to a 0. These bits are
not reset by the Soft Reset function.
Input Clock
11.0 MHz
12.0 MHz
12.5 MHz
32.0 MHz
36.0 MHz
37.5 MHz
48.0 MHz
8.5 MHz
9.0 MHz
113 of 133
Table 9,
page 113 describes the appropriate CKSEL input and
Main Divider
Divide-by-4
Divide-by-4
Divide-by-4
Divide-by-4
NA
NA
NA
NA
NA
DD
CDC Register
(divide by 6), yielding an
142 (8Dh)
200 (C7h)
208 (CFh)
200 (C7h)
SS
150 (95h)
183 (B6h)
133 (84h)
150 (95h)
156 (9Bh)
or V
DD
based on the desired
20 kHz Clock
19.95 kHz
20.03 kHz
20.03 kHz
20.05 kHz
20.03 kHz
20.0 kHz
20.0 kHz
20.0 kHz
20.0 kHz
January 2008
Revision 4.1