vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 104

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

Operating Notes for the Master Serial Interface
Revision 4.1
January 2008
Encoded Two-Wire Serial Commands
52h - Read byte with stop, no acknowledge (used at the end of read telegrams)
54h - Read byte with acknowledge (used for middle bytes during sequential reads)
58h - Write byte (used for end of address writes or middle bytes of sequential writes)
59h - Write byte with start (used for the beginning of all telegrams and restarts)
5Ah - Write byte with stop (used for end of write telegrams)
60h - Soft reset
The sequence for normal two-wire serial protocol compliant write operations is:
1.
2.
3.
Bit
1
0
Issue start bit, send the slave device address and write bit (0) in the LSB.
Send the slave device's register address, this can zero bytes or in some slave devices this may be multiple
Send the byte to be written to the slave device, followed by a stop bit.
bytes.
Pseudo-code to perform two-wire serial protocol compliant writes
using this core:
Send slave device address:
1) <{slave_address[6:0],1'b0}>
2)
3)
4)
did not respond
Send register address:
5)
6)
7)
8)
did not acknowledge
Bit Label
STO
STA
Write 59h to the MIC register (command)
Poll the MIS register (status) until bit 0 = 1
Test bit 1, if set continue, if clear then the slave device
<slave's register address>
Write 58h to MIC register (command)
Poll the MIS register (status) until bit 0 = 1
Test bit 1, if set continue, if clear then the slave device
Access
R/W
R/W
Description
Stop Condition
This bit controls the STOP condition of a serial transfer.
Setting this bit directs the master serial interface to generate a stop bit
sequence (rising edge on SDA while SCL is HIGH) after transferring the
immediate byte. This should only be done to end a telegram.
After a reset or power on, this bit is cleared.
Start Condition
This bit provides control for the start condition of a serial transfer.
Setting this bit directs the master serial interface to generate a start bit
sequence (falling edge on SDA while SCL is HIGH) prior to transferring the
immediate byte. This operation should be initiated at the beginning of a
telegram and as required for restarts during read transactions.
After a reset or power on, this bit is cleared.
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MID register (data)
MID register (data)
VSC055-01
Data Sheet