vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 107

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
3.2.93 ECh: Master Interface Low-Level Control (MILC)
3.2.94 EDh: Master Interface Status (MIS)
The following table shows the bit assignments for the Master Interface Low-Level Control register.
The following table shows the bit assignments for the Master Interface Status register.
Register Name:
Address:
Reset Value:
Bit
7:1
0
Register Name:
Address:
Reset Value:
Bit
7:2
1
0
Bit Label
RES
SCLO
Bit Label
RES
ACKR
DONE
MILC
ECh
XXXX_XXX1b
MIS
EDh
XXXX_XX00b
Access
R
R/W
Access
R
R
R
Description
Reserved.
Serial Clock Output
This bit provides low-level control of the master interface SCL output. This
register bit provides set or clear capability on the SCL output control register
within this core. As such, writing any value to this register may interfere with
automatic interface activity. During normal core operation, this register should
not be written. Reading this register bit returns the SCL output value that this
core is currently driving on the serial bus.
After a reset or power on, this bit is set (SCL inactive).
Description
Reserved.
Acknowledge Received
This bit indicates if an acknowledge is received after a write operation.
1: An acknowledge has been received.
0: An acknowledge has not been received.
After a reset or power on, this bit is cleared.
Transfer Complete
This bit indicates when the current transfer is complete.
1: the current transfer is complete.
0: the current transfer is not complete.
After a reset or power on, this bit is cleared.
Note: The status bits provided in this register are also effectively available by
reading the MIC register (bit 2, ACK and bit 4, GO). The intention of this
optional register is to provide a simple programming model with only the
required status bits included so that other bit positions do not need to be
masked off to determine the result of a two-wire serial transfer operation.
During master serial interface write operations, it is possible to write the MID
(data) and MIC (command) registers, perform a restart, read the current
address (the MILC register), and then poll the MIS (status) register to
determine if the current write operation is complete.
107 of 133
January 2008
Revision 4.1