vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 108

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

3.2.95 EEh: Master Interface Read Data (MIRD)
3.2.96 F0h-F7h: Bit Control Port 7 (BCP70-BCP77)
Revision 4.1
January 2008
This register allows a sequential read operation of the MIC (command), MILC (low-level control, delay to
allow transfer to complete), MIS (status), and MIRD (read data) registers by an external microcontroller to
form a complete read transfer. It returns the same data as the MID (data) register
The following table shows the bit assignments for the Master Interface Read Data register.
These eight registers provide individual bit control for the Port 7 I/O pins. All register bits are identical
from a control and status perspective, with the only difference being the individual I/O pin controlled and
the presence of the bypass function. The Data Direction (bit 1) and General-Purpose Data (bit 0) bits are
effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths.
These eight registers function the same as the eight Bit Control Port 0 registers except that they relate to
the Port 7 I/O pins. For information about the functionality of the Bit Control Port 0 registers, see
87h: Bit Control Port 0 (BCP00-BCP07),”
The following table shows the bit assignments for the Bit Control Port 7 registers.
Register Name:
Address:
Reset Value:
Bit
7:0
Register Name:
Address:
Reset Value:
Bit
7
Bit Label
MD7-0
Bit Label
PTE
BCP70-BCP77
F0h-F7h
0000_001Xb
MIRD
EEh
0000_0000b
Access
R/W
Access
R
Description
Pulse Train Enable
This bit, along with the FS bits, enables one of eight pulse train circuits
controlled by the pulse train registers, PTC00 through PTC71 (70h through
7Fh), as the output drive function for this I/O pin.
When this bit is set, the FS bits select one of eight pulse train circuits instead of
the normal fixed-rate LED flashing circuits or the normal output drive mode. For
the various LED drive control modes, see
After a reset or power on, this bit is cleared.
Description
Master Interface Data
These eight read-only bits provide the data value received from serial read
operations.
After a reset or power on, these bits are cleared.
108 of 133
page 78.
Table 5,
.
page 80.
VSC055-01
Data Sheet
“80h-