sza1000 NXP Semiconductors, sza1000 Datasheet - Page 8

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sza1000

Manufacturer Part Number
sza1000
Description
Qic Digital Equalizer
Manufacturer
NXP Semiconductors
Datasheet

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Parallel state bus
All internal digital signals can be monitored via an 8-bit
parallel bus. An external DAC or an evaluation tool such as
a phase error logger for TIA (Time Interval Analyzer),
drop-out and symmetry measurements can be connected
to this bus for evaluation purposes (see Table 34).
Write equalization
This circuit has an independent clock input WEQCLK at
pin 9.
Write equalization can be programmed to conform to a
number of formats including QIC 3010, QIC 3020,
QIC 3080, QIC 3095, QIC 5010, Travan 2, Travan 3 and
Travan 4.
This is achieved by programming the circuit to divide a
channel bit-cell into 2, 3 or 6 time slots (see Tables 13
and 14). The external WEQ clock frequency should be
selected such that an integer number of between 1 and 8
clock periods fits in a time slot (see Tables 18 and 19).
The width and position of the inserted write pulse can be
programmed (see Tables 15 to 17).
The write equalization circuit input and output signals can
be independently programmed to be in either WD or WDI
format (see Table 15).
1998 Feb 16
QIC digital equalizer
8
For QIC 3010 or 3020, the recording signal is typically
generated by a circuit that uses a separate crystal.
An input buffer with variable delay is used to prevent errors
occurring in the recorded signal. This buffer is set to its
nominal position when writing begins.
Signals longer than a data block can be recorded during
formatting. To avoid overloading the time buffer, the circuit
can resynchronize automatically during gaps in the
QIC 3010 or 3020 format.
Serial interface
The serial interface uses 8-bit addresses and 8-bit data.
Its timing is shown in Fig.5. IC mode settings, filter
coefficients, scale factors and thresholds can be loaded
via the serial interface.
Measured signal amplitude, for example Burst level
measurement at QIC 3095 or AGC control by the
microcontroller, and the actual PLL frequency can be read
via the serial interface. To read data from the status
registers, hex address FF must be transmitted along with
the required data code. The IC will then respond with the
contents of the appropriate 8-bit status register
(see Table 44).
Product specification
SZA1000

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