sza1000 NXP Semiconductors, sza1000 Datasheet - Page 6

• Manufacturer Part Number: sza1000
• Description: Qic Digital Equalizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Clock oscillator and divider
The clock source for the SZA1000 can be a crystal
connected between pins 6 and 7, or an external clock
signal connected to pin 6. This clock frequency is divided
by a number programmable between 1 and 8
(see Tables 27 and 28). The resulting frequency, f
used as clock input to all on-chip circuits except the write
equalizer. The frequency of the PACLK output signal
(pin 29) is equal to f
ADC
The 8-bit ADC has a differential input. The total ADC
conversion range is 1.6 V (p-p; differential). The ADC
sample rate is equal to f
High-pass filter after the ADC
This is a first order filter with a cut-off frequency of
It removes the DC component of the signal.
Low-pass filter
This low-pass filter is an even symmetrical FIR (Finite
Impulse Response) filter. The number of taps depends on
the sample rate reduction factor R (see Tables 30 and 31).
The filter has 8 taps for R = 1 or 14 taps for R = 2 (see
Table 7). The middle taps have a fixed coefficient value of
+128, the coefficients of the other taps are programmable
in the range 128 to +127 (see Table 6).
FIR
This transversal filter has 6 taps with the sample rate equal
to f
(R = 2). Tap 10 has a fixed coefficient value of +64, the
coefficients of the other taps are programmable between
sections. The position of each tap can be selected from a
subset of the 20 possible positions (see Tables 3 and 4).
Interpolator
If a sample rate of
(R = 2), it is increased once again to f
1998 Feb 16
64 and +63 (see Table 2). The filter has 19 signal delay
QIC digital equalizer
s
(R = 1), or 11 taps with the sample rate equal to
1
s
2
.
f
s
has been selected for the FIR
s
.
s
at the interpolator.
s
, is
------------ -
1608
f
1
s
2
f
s
6
Amplitude detector
This circuit has a separate rectifier and a positive and
negative peak detector.
Typical rise time (0 to 70%) for a normal MFM or
RLL 1,7 code input signal is
(100 to 30%) is programmable between
(see Tables 10 and 11).
The output is an 8-bit number that can be polled via the
serial interface. In addition, the peak-to-peak value is
calculated and filtered by a first order low-pass filter with a
cut-off frequency of
Both the filtered and unfiltered amplitudes can be read via
the serial interface (see Table 44) or via the parallel output
bus.
Amplitude qualifier
A peak is considered valid if its amplitude is above a
qualification threshold. Separate qualification thresholds
are used for the positive and negative peaks. Each
threshold is the greater of:
Gap detector
When the peak-to-peak amplitude of the measured signal
is below a preset limit (GAP_THRESH; control register
address 28), the gap detector output is HIGH, otherwise
LOW (GAP output on pin 21 must be selected; see
Table 22).
a programmable level (QUAL_FIX_ POS and
QUAL_FIX_NEG; control register addresses 24 and 25)
a programmable fraction (
see Tables 9 and 12) of the peak amplitude of the
incoming signal.
------------ -
3217
f
s
1
--- -
f
1
s
2
,
, typical decay time
3
8
,
1
4
Product specification
,
1
8
500
--------- -
SZA1000
or 0;
f
s
and
400
--------- -
f
s