cxd2548r Sony Electronics, cxd2548r Datasheet - Page 84

• Manufacturer Part Number: cxd2548r
• Description: Cd Digital Signal Processor With Built-in Digital Servo And Dac
• Manufacturer: Sony Electronics

§4-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz and loaded. The MIRR and
DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of these envelope waveforms.
The MIRR signal is generated by comparing this MIRR comparator level with the waveform generated by
subtracting the bottom hold value from the peak hold value. (See Fig. 4-6.)
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 4-7.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
–Bottom Hold
Peak Hold
Bottom Hold
–Peak Hold1
Peak Hold
Peak Hold1
Peak Hold2
Peak Hold2
MIRR
DFCT
RF
RF
Fig. 4-7.
Fig. 4-6.
– 84 –
SDF
MIRR Comp
(Mirror comparator level)
H
L
(Defect
comparator level)
H
L
CXD2548R