cxd2548r Sony Electronics, cxd2548r Datasheet - Page 14

• Manufacturer Part Number: cxd2548r
• Description: Cd Digital Signal Processor With Built-in Digital Servo And Dac
• Manufacturer: Sony Electronics

Contents
[1] CPU Interface
[2] Description of CD Signal Processing and DAC System Commands and Subcode Interface
[3] Description of Other CD Signal Processing and DAC System Functions
[4] Description of Servo Signal Processing System Functions and Commands
[5] Application Circuit
§1-1. CPU Interface Timing ...................................................................................................................... 15
§1-2. CPU Interface Command Table . ..................................................................................................... 16
§1-3. CPU Command Presets .................................................................................................................. 25
§1-4. Description of SENS Signals ........................................................................................................... 30
§2-1. Description of Commands and Data Sets ....................................................................................... 31
§2-2. Subcode Interface ........................................................................................................................... 50
§3-1. Description of DSP Operating Modes ............................................................................................. 55
§3-2. Frame Sync Protection .................................................................................................................... 57
§3-3. Error Correction ............................................................................................................................... 57
§3-4. DA Interface .................................................................................................................................... 58
§3-5. Digital Out ........................................................................................................................................ 60
§3-6. Servo Auto Sequence ..................................................................................................................... 60
§3-7. Asymmetry Compensation .............................................................................................................. 67
§3-8. Channel Clock Regeneration by the Digital PLL Circuit .................................................................. 68
§3-9. Digital CLV ...................................................................................................................................... 70
§3-10. 1-bit DAC Block ............................................................................................................................... 71
§3-11. LPF Block ........................................................................................................................................ 73
§3-12. Setting the Playback Speed for the CD-DSP and 1-bit DAC Blocks ............................................... 74
§4-1. General Description of the Servo Signal Processing System ......................................................... 75
§4-2. Digital Servo Block Master Clock (MCK) ......................................................................................... 76
§4-3. AVRG Measurement and Compensation ........................................................................................ 76
§4-4. E:F Balance Adjustment Function ................................................................................................... 78
§4-5. FCS Bias Adjustment Function ....................................................................................................... 78
§4-6. AGCNTL Function ........................................................................................................................... 80
§4-7. FCS Servo and FCS Search ........................................................................................................... 82
§4-8. TRK and SLD Servo Control ........................................................................................................... 83
§4-9. MIRR and DFCT Signal Generation ................................................................................................ 84
§4-10. DFCT Countermeasure Circuit ........................................................................................................ 85
§4-11. Anti-Shock Circuit ............................................................................................................................ 85
§4-12. Brake Circuit .................................................................................................................................... 86
§4-13. COUT Signal ................................................................................................................................... 87
§4-14. Serial Readout Circuit ..................................................................................................................... 87
§4-15. Writing the Coefficient RAM ............................................................................................................ 88
§4-16. PWM Output .................................................................................................................................... 88
§4-17. Servo Status Changes Produced by the LOCK Signal ................................................................... 90
§4-18. Description of Commands and Data Sets ........................................................................................ 90
§4-19. List of Servo Filter Coefficients ...................................................................................................... 102
§4-20. FILTER Composition ..................................................................................................................... 104
§4-21. TRACKING and FOCUS Frequency Response ............................................................................ 111
§5-1. Application Circuit .......................................................................................................................... 112
(a)
(b)
(c)
CLV-N Mode .................................................................................................................................... 55
CLV-W Mode ................................................................................................................................... 55
CAV-W Mode .................................................................................................................................. 55
Explanation of abbreviations
AVRG:
AGCNTL: auto gain control
FCS:
TRK:
SLD:
DFCT:
– 14 –
Average
Focus
Tracking
Sled
Defect
CXD2548R