cxd2548r Sony Electronics, cxd2548r Datasheet - Page 7

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cxd2548r

Manufacturer Part Number
cxd2548r
Description
Cd Digital Signal Processor With Built-in Digital Servo And Dac
Manufacturer
Sony Electronics
Datasheet

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Notes) • PCMD is a MSB first, two's complement output.
Pin
No.
110
111
112
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and negative pulse. It is the signal before
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
• The GFS signal goes high when the frame sync and the insertion timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs (during normal speed).
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
AV
AVss2
Vss0
Symbol
sync protection.
EFM signal transition point coincide.
DD
2
I/O
R ch, analog power supply.
R ch, analog GND.
Digital GND.
– 7 –
Description
CXD2548R

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