em78p134n ELAN Microelectronics Corp, em78p134n Datasheet - Page 38

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em78p134n

Manufacturer Part Number
em78p134n
Description
8-bit Microcontroller With Otp Rom
Manufacturer
ELAN Microelectronics Corp
Datasheet
EM78P134N
8-Bit Microcontroller with OTP ROM
32 •
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Figure 5-9). The RETI instruction ends the interrupt
routine and enables the global interrupt (execution of ENI).
When an interrupt is generated by the Timer clock / counter (if enabled), the next
instruction will be fetched from Address 009H, and 00FH (TCC and Timer 1 respectively).
Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers will be saved by the hardware. If another interrupt occurs, ACC, R3, and R4 will
be replaced by the new interrupt. After the interrupt service routine is completed, ACC,
R3, and R4 registers are restored.
In EM78P134N, each individual interrupt source has its own interrupt vector as
depicted in the table below.
Interrupt sources
Interrupt Vector
ENI/DISI
00CH
00FH
003H
006H
009H
External interrupt
Port 6 pin change
TCC overflow interrupt
Comparator interrupt
Timer 1 (PWM) overflow interrupt
Figure 5-10 Interrupt Backup Diagram
Interrupt Status
(This specification is subject to change without further notice)
ACC
R3
R4
Product Specification (V1.6) 06.02.2010
*Priority : 1 = highest ; 5 = lowest priority
Interrupt
occurs
RETI
STACKACC
STACKR3
STACKR4
Priority*
1
2
3
5
4

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