em78p134n ELAN Microelectronics Corp, em78p134n Datasheet - Page 20
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em78p134n
Manufacturer Part Number
em78p134n
Description
8-bit Microcontroller With Otp Rom
Manufacturer
ELAN Microelectronics Corp
Datasheet
1.EM78P134N.pdf
(62 pages)
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EM78P134N
8-Bit Microcontroller with OTP ROM
14 •
5.2.5 IOC7 (TMRH: Most Significant Bits of the PWM Timer)
Bits 7 ~ 6 (unused): unused bits, set to 0 all the time.
Bits 5 ~ 4 (TMR[9]~TMR[8]): most significant bits of the PWM timer, read-only bit.
Bits 3 ~ 2 (PRD[9]~PRD[8]): most significant bits of the PWM time period.
Bits 1 ~ 0 (DT[9]~DT[8]): most significant bits of the PWM duty cycle.
5.2.6 IOC8 (TMRL: Least Significant Byte of the PWM Timer)
The content of IOC8 is read-only.
5.2.7 IOC9 (PRDL: Least Significant Byte of the PWM Time Period)
The content of IOC9 is the time period (time base) of PWM. The PWM frequency is the
reverse of the period. Most Significant Bits (Bits 9, 8) of the PWM Period Cycle are
located in IOC7<3, 2>
5.2.8 IOCA (DTL: Least Significant Byte of the PWM Duty Cycle)
A specified value keeps the PWM output to remain high until the value matches with
TMR.
5.2.9 IOCB (Pull-down Control Register)
Bit 7 (unused): Unused bit, set to 0 all the time.
Bit 6 (/PD62): Control bit used to enable pull-down of the P62 pin.
Bit 5 (/PD61): Control bit used to enable pull-down of the P61 pin.
Bit 4 (/PD60): Control bit used to enable pull-down of the P60 pin.
Bits 3 ~ 0 (/PD53): Unused bits, set to 0 all the time.
The IOCB Register is both readable and writable.
TMR[7]
PRD[7]
DT[7]
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
TMR[6]
PRD[6]
DT[6]
/PD62
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
0
0: Enable internal pull-down
1: Disable internal pull-down
.
TMR[9]
TMR[5]
PRD[5]
/PD61
DT[5]
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
TMR[8]
TMR[4]
PRD[4]
/PD60
DT[4]
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
(This specification is subject to change without further notice)
PRD[9]
TMR[3]
PRD[3]
DT[3]
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
0
Product Specification (V1.6) 06.02.2010
PRD[8]
TMR[2]
PRD[2]
DT[2]
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
0
TMR[1]
PRD[1]
DT[9]
DT[1]
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
0
TMR[0]
PRD[0]
DT[8]
DT[0]
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
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