S12ATD10B8CV2 MOTOROLA [Motorola, Inc], S12ATD10B8CV2 Datasheet - Page 65
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S12ATD10B8CV2
Manufacturer Part Number
S12ATD10B8CV2
Description
MC9S12DT128 Device User Guide V02.09
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.S12ATD10B8CV2.pdf
(138 pages)
- Current page: 65 of 138
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MC9S12DT128 Device User Guide — V02.09
2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15]
PAD15 is a general purpose input pin and analog input of the analog to digital converter ATD1. It can act
as an external trigger input for the ATD1.
2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]
PAD14 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD1.
2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7]
PAD7 is a general purpose input pin and analog input of the analog to digital converter ATD0. It can act
as an external trigger input for the ATD0.
2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]
PAD6 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD0.
2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
(low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this
pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an
external clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since
this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is
an oscillator circuit on EXTAL and XTAL.
65
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