TSS463-AAR ATMEL [ATMEL Corporation], TSS463-AAR Datasheet - Page 6

• Manufacturer Part Number: TSS463-AAR
• Description: VAN Data Link Controller with Serial Interface
• Manufacturer: ATMEL [ATMEL Corporation]

SCLK: Serial Clock
MOSI: Master Out Slave In
MISO: Master In Slave Out
SS: Slave Select
SPI Protocol
6
TSS463-AA
Figure 3. SPI Data Stream
The master device provides the serial clock for the slave devices. Data is transferred
synchronously with this clock in both directions. The master and the slave devices
send/receive a data byte during an eight-clock pulse sequence.
The MOSI pin is the master device data output (CPU) and the slave device data input
(TSS463AA). Data is transferred serially from the master to the slave on this line; most
significant bit (MSB) first, least significant bit (LSB) last.
The MISO pin is configured as the slave device data output (TSS463AA) and as master
device data input (CPU). When the slave device is not selected (SS = 1), this pin is in
high impedance state.
The SS pin is the slave chip select. It is low active. A low state on the Slave Select input
allows the TSS463AA to accept data on the MOSI pin and send data on the MISO pin.
The Slave Select signal must not toggle between each transmitted byte and should be
left at a low level during the whole SPI frame. SS must be asserted to inactive high level
at the end of the SPI frame.
As mentioned before, if SS is not asserted, MISO pin is in a high impedance state and
incoming data is not driven to the serial data register.
The general format of the data communication in the SPI frame between the TSS463AA
and the host is a bit-for-bit exchange on each SCLK clock pulse. Data is arranged in the
TSS463AA such that the significance of a bit is determined by its position from the start
for output and from the end for input, most significant bit (MSB) is sent first. Bit
exchanges in multiples of 8 bits are allowed.
The Idle Clock Polarity (CPOL) and the Clock Phase (CPHA) are not programmable: the
CPOL and CPHA values to be programmed in the master (CPU) are CPOL = CPHA = 1.
This is available for all modes. Waveforms with transmit and sample points are shown in
Figure 6.
SCLK
MOSI
MISO
SS
SPI 8 Pulses
0x55
0x66
4205B–AUTO–12/04