TSS463-AA ATMEL Corporation, TSS463-AA Datasheet
TSS463-AA
Related parts for TSS463-AA
TSS463-AA Summary of contents
Page 1
... In addition, the bus interface has three separate inputs with automatic source diagno- sis and selection. The interface allows for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. VAN Data Link Controller with Serial Interface TSS463-AA Rev. 4205A–AUTO–03/03 ...
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... Block Diagram TSS463-AA 2 4205A–AUTO–03/03 ...
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... XTAL2 6 TEST/VSS 7 CKOUT 8 RXD1 9 RXD2 10 RXD0 11 TXD 12 GND 13 RESET 14 SCLK 15 MOSI 16 TSS463-AA TOP VIEW 16 MOSI 15 SCLK 14 RESET 13 GND 12 TXD 11 RXD0 10 RXD2 RXD1 9 Pin Function SPI/SCI Data Output SPI/SCI Slave Select (active low) Interrupt (active low power supply Crystal oscillator or clock input pin from MHz ...
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... Figure 1. Typical Application With Motorola SPI Mode Remaining pins mC PORT X.Y RESET TSS463-AA 4 The TSS463AA is a microprocessor controlled line controller for the VAN bus. It can interface to virtually any microprocessor which includes SPI or SCI interface. • The TSS463AA provides one full Motorola compatible SPI interface. ...
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... Figure 5. One pin is needed for the serial clock (SCLK), two pins for data communication MOSI and MISO and one pin for Slave Select (SS). TSS463-AA ® SPI mode and “9 bits to SPI 8 Pulses ...
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... SCLK: Serial Clock MOSI: Master Out Slave In MISO: Master In Slave Out SS: Slave Select SPI Protocol TSS463-AA 6 Figure 3. SPI Data Stream SCLK MOSI MISO SS The master device provides the serial clock for the slave devices. Data is transferred synchronously with this clock in both directions. The master and the slave devices send/receive a data byte during an eight-clock pulse sequence ...
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... When the master (CPU) conducts a write, it sends an address byte, a control byte and data bytes on its MOSI line. The slave device (TSS463AA) will send, if well-synchro- nized, “0xAA” during the address byte and “0x55” during the control byte on its MISO line. TSS463-AA CPOL = CPHA = 1 Data Sample Points 0x55 ...
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... PORT X.z IRQ RESET (1) XTAL1 TSS463-AA 8 When the master (CPU) conducts a read, it sends an address byte, a control byte and dummy characters ("0xFF" for instance) on its MOSI line. In the case of a VAN mes- sages RAM read (VAN frame received), the first data byte sent back by the TSS463AA on its MISO pin is the data length so the master knows how many dummy characters it must send to read the VAN frame properly ...
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... The SS pin is the slave chip select low active. A low state on the Slave Select input allows the TSS463AA to accept data on the MOSI pin and send data on the MISO pin. TSS463-AA SCI 9 Pulses 0x55 ...
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... SS 4 Xtal Min ( MHz) SCI Mode TSS463-AA 10 The Slave Select signal must not toggle between each transmitted byte and therefore, should be left at a low level during the whole SCI frame. SS must be asserted to inactive high level at the end of the SCI frame. ...
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... It is important to note that even after a reset on the RESET pin, the user should wait for 12 clock periods before sending the "Initialization Sequence" in order to select the SPI or SCI mode (because the default mode after a hardware reset is the Motorola SPI mode). TSS463-AA Data 15 Xtal Min 12 Xtal Min ...
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... Figure 9. Asynchronous Software Reset with UART Intel Mode SCLK MOSI SS Reset Internal Pulse Oscillator TSS463- XTAL Min 0xFF An oscillator is integrated in the TSS463AA, and consists of an inverting amplifier of which the input is XTAL1 and the output XTAL2. A parallel resonance quartz crystal or ceramic resonator must be connected to these pins ...
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... TSS463-AA 4 MHz 2 MHz KTS/s Kbits/s KTS/s 250 200 125 125 100 62.50 62.50 50 31.25 31.25 25 15.625 15.625 12.5 7.813 7.813 6.25 3.906 3.906 3.125 1.953 1 ...
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... Figure 10. CSMA/CD Arbritration Node a: TxD Node b: TxD Node c: TxD On Bus: DATA TSS463-AA 14 There are three line inputs and one line output available on the TSS463AA. Which of the three inputs to use is either programmable by software or automatically selected by a diagnosis system. The diagnosis system continuously monitors the data received through the three inputs, and compares it with each other and the selected bitrate ...
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... Figure 12 shows a normal VAN bus frame initiated with a Start of Frame (SOF) sequence shown in Figure 14. The SOF can only be transmitted by an autonomous module. During the preamble, the TSS463AA will synchronize its bit rate clock to the data received. TSS463-AA Frame Data Check ...
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... TSS463-AA 16 Figure 14. Framing Sequences VAN BUS SEQUENCE VAN BUS END OF DATA SEQUENCE NUMBER OF PRESCALED CLOCKS 0 16 When the complete SOF sequence has been transmitted or received, the circuit will start the transmission or reception of the identifier field. All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are transmitted using enhanced Manchester code ...
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... The next field is the FCS field. This field bit CRC checksum defined by the follow- ing generator polynomial g(x) of order 15 g(x The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is performed before transmission. TSS463- ...
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... Frame Examples TSS463-AA 18 However, since the CRC is calculated automatically from the identifier, command and data fields by the TSS463AA, therefore, the user should not be concerned with the cir- cuit. When the frame check sequence has been transmitted, the transmitting module must transmit an End of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to terminate the transfer ...
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... Dominant from Transmitter RTR : Dominant from Transmitter ACK : Absent from Transmitter and from Receiver because RAK is Dominant 4205A–AUTO–03/03 IDENTIFIER DATA IDENTIFIER DATA - (*) Manchester bit IDENTIFIER DATA IDENTIFIER DATA - (*) Manchester bit TSS463-AA CRC EOF CRC EOF CRC EOF CRC EOF 19 ...
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... EXT : Recessive from Requestor RAK : Recessive for acknowledge from Requestor R/W : Recessive from Requestor RTR : Recessive from Requestor - (*) Manchester bit ACK : Absent from Requestor and Positive from Requestee because RAK is Recessive TSS463-AA 20 IDENTIFIER DATA IDENTIFIER DATA IDENTIFIER IDENTIFIER CRC CRC - (*) Manchester bit ...
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... Recessive from Replyer RAK : Recessive for acknowledge from Replyer R/W : Recessive from Replyer RTR : Dominant from Replyer ACK : Absent from Replyer and Positive from Receiver because RAK is Recessive 4205A–AUTO–03/03 IDENTIFIER DATA IDENTIFIER DATA - (*) Manchester bit TSS463-AA CRC EOF CRC EOF 21 ...
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... Diagnosis System Diagnosis States TSS463-AA 22 The purpose of the diagnosis system is to detect any short or open circuits on either the DATA or DATA lines and to permit possible, to carry the communications on the non-defective line. The diagnosis system is based on the assumption that three separate line receivers are connected to the VAN bus see Figure 1: • ...
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... Synchronous diagnosis The synchronous diagnosis counts the number of edges on the data input connected to the reception logic during one SDC period. If there are less than four edges during one SDC period, the diagnosis mode will change to the major error mode. TSS463- timeslot). 23 ...
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... Signals RI Signal (Return to Idle) SDC Signal (Synchronous Diagnosis Clock) TIP Signal (Transmission in Progress) TSS463-AA 24 • Transmission diagnosis The transmission compares RxD1 and RxD2 inputs (through the input comparators and the filters) with the data transmitted on TxD output time when the transmission logic generates a dominant - recessive transition, the inputs can give different values ...
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... Four programming modes determine how to use the three different inputs and the diag- nosis system. • 3 specified selection modes • 1 automatic selection mode Table 4. Programming Modes Ma Mb Operating Mode 0 0 Differential communication 0 1 Degraded communication on RxD2 (DATA Degraded communication on RxD1 (DATA Automatic selection according the diagnosis status TSS463-AA 25 ...
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... Value after RESET is found after register name value is given, the register is not initialized at RESET. TSS463-AA 26 The TSS463AA memory map consists of three different areas, the Control and Status registers, the Channel registers and the Message data (or Mailbox). ...
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... RxD inputs MR3 MR2 MR1 Read/Write register. Default value after reset: 0x02 These bits allow the user to control the amount of retries the circuit will perform if any errors occurred during transmission. TSS463- CD0 PC 0 IVTX ...
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... VER[2:0] = 001 TSS463-AA 28 Table 5. Retries MR [3:0] Max retries 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Note: Bus contention is not regarded as an error and an infinite number of transmission attempts will be performed if bus contention occurs continuously. ...
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... For each module, determine the largest interframe spacing, LIFS (*). 2. For the whole network, get the maximum LIFS, MAX-LIFS. 3. SDC period > MAX-LIFS. (*) IFS min Example: For VAN frame speed rate = 62,5 KTS µs), SDC >100 ms => 100 µs = 6250, divider chosen: 8192, SDC [3:0] = 0111. TSS463- SDC0 Ma ...
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... Ma, Mb: Operating Mode Command Bits ETIP: Enable Transmission In Progress ESDC: Enable System Diagnosis Clock Command Register (0x03) GRES: General Reset SLEEP: Sleep Command TSS463-AA 30 Table 7. Diagnosis System Command Bits The Transmission In Progress (TIP) tells the diagnosis system to enable transmission diagnosis ...
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... Default mode at reset • Sa and Sb Diagnosis System Status Bits TSS463- TXG Communication Indication Nominal mode, differential communication Degraded over DATA, fault on DATA Degraded over DATA, fault on DATA Major error, fault on DATA and DATA 1 ...
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... IDT [3:0]: Last Message Status Register (0x06) NRTR [3:0]: IDTR [3:0]: TSS463-AA 32 • Sc: As soon as one of the three inputs (RxD2, RxD1, RxD0) differs from the others in the input comparison analysis performed by the diagnosis system set. The only ways to reset this status bits through the RI signal or a general reset. ...
Page 33
... FCSE indicates a mismatch between the FCS received and the FCS calculated One: FCSE active Zero: FCSE inactive ACKE indicates a physical violation or collision on ACK field of the frame when the TSS463AA is a producer. One: ACKE active Zero: ACKE inactive TSS463- FCSE ...
Page 34
... CV: Code Violation FV: Frame Violation TSS463-AA 34 Figure 23. ACKE Status bit RAK = 0 EOD field Expected Received Received Received RAK *RAK: Bit of the Frame COMMAND Field EOD field Expected Received Received Received CV indicates: • either a Manchester code violation (2 identical TS on Manchester bit physical violation (transmitted bit “ ...
Page 35
... Zero: No status flag. This flag is set only when the Max number of transmission ( [3:0]) is reached with error of transmission. One: Status flag activated Zero: No status flag. Figure 25. Exceeded Retry with MR[3.. 1st TX 2nd TX TSS463-AA DLC: Consumer ACK field ACK field ...
Page 36
... TOKE: Transmission OK Enable REE: Reception Error Enable ROKE: Reception “with RAK” OK Enable RNOKE: Reception “with no RAK” OK Enable Interrupt Reset Register (0x0B): TSS463-AA 36 One: Status flag activated Zero: No status flag. One: Status flag activated Zero: No status flag. One: Status flag activated Zero: No status flag ...
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... TOK RE Flag Flag Write Write TOKE REE TER TOKR RER SOF ID+COM+DATA+CRC Write “Message Status” TSS463-AA ROK RNOK Flag Flag Write Write ROKE RNOKE ROKR RNOKR 6 TS Line Status Register (0x04 Write “IT Status Register” Write “Last error Register” ...
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... Channel Registers TSS463-AA 38 There is a total of 14 channel register sets, each occupying 8 bytes for addressing sim- plicity, integrated into the circuit. Each set contains two 2 x 8-bit registers for the identifier tag, identifier mask and command fields plus two 1 x 8-bit registers for DMA pointers and message status ...
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... However, the identifier, mask, error and transmitted status used will be that of the origi- nally matched channel. In any case link is intended, the three high bits of M_P [6:0] should be set to 0. TSS463- ...
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... Abort Command CHTx: Channel Transmitted and Transmit Enable Command CHRx: Channel Received and Receive Enable Command TSS463-AA 40 This allows several channels to use the same actual reception buffer in Message DATA RAM, thus diminishing the memory usage. Note: Only 1 level of link is supported. ...
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... ID_M 11 ID_M 10 ID_M 9 ID_M 8 • Read/Write registers. A value of 1 indicates comparison enabled. A value of 0 indicates comparison disabled. Example: – ID_M[11:0] = 0x0FF8 – Acceptance: ID’s from 0x0FF8 up to 0x0FFF TSS463- ID_M 7 ID_M 6 ID_M 5 ID_M 4 ...
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... CHER CHTx CHRx SOF ID [11..0] Received DATA Frame, immediate or deffered reply TSS463-AA 42 The mailbox contains all the messages received transmitted. Each messages is link to a channel. The Mailbox RAM area has 128 bytes and is mapped from 0x80 to 0xFF (see Section “Mapping”, page 26 ). ...
Page 43
... This bit is the RNW bit coming from the COM field of the received frame. This bit is the RTR bit coming from the COM field of the received frame. If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1, even if the reserved length (Message Length and Status Register) is larger. TSS463-AA Message Pointer Register M_P [6..0] DRAK ...
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... Data Frame Immediate Reply Deferred Reply Data Frame Immediate Reply Deferred Reply P: Producer (*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous. Message Data (string pointed by: Message Pointer Register + 1) TSS463-AA 44 Commu- Node x Node A nication ...
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... TSS463AA will set the message type to the after transmission state. When this message type is programmed, the TSS463AA will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. TSS463-AA Transmit Message RTR CHTx ...
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... TSS463-AA 46 The second case is that another module on the bus replies with an in-frame reply. In this case the message type will pass immediately into the after reception state, without pass- ing the after transmission state. Reply Request Message without transmission RNW Initial setup ...
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... Message Length and Status Register (base_address + 0x03). These three commands are available only when the TSS463AA is a producer. Figure 30. Transmit Function Disable of Current Ch. Yes Decrement Retry Counter Abort Yes TSS463-AA Activate Ch. Enabled in No Xmit Mode ? Yes Select the Lowest Ch. Number and Load ”Max - Retries” Abort Activated on Current Ch ...
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... Retries Rearbitrate Typical Example TSS463-AA 48 The purpose of the retries feature is to provide, for the user, the capability of retrying a transmit request in case of failure, when a node tries to reach another node, either on normal DATA frame or on REPLY REQUEST frame. The maximum number of retries is programmable through MR[3:0] of the Transmit Con- trol Register (0x01). When a channel is enable – ...
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First attempt (Load Max-retries) Xmit Ch8 Rearbitrate (Activate Ch5) Ex: FCS Error * (not seen by application) Xmit Ch5 (Load Max-retries) Idle command Set CHTx/Ch5 & IT ROK First attempt (Load Max-retries) Xmit Ch8 Ex: FCS Error (Retries - 1) ...
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... Figure 33. Disable Channel After Rearbitrate Delay Viol In this case, the TSS463AA completes the current attempt (Ch8) and let the transmission go on the new channel (Ch5 if validated), otherwise it stops all attempts on the current channel. Abort TSS463-AA 50 Ex: ACK Error (not seen by application) Delay Viol ...
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Reset Ch s Initialization Activate Abort Ch0 (before Xmit) Set CHTx/Ch0 Abort Ch13 (before Xmit) Xmit Ch4 Abort Ch4 (during Xmit) Set CHTx/Ch4 &IT ROK Xmit Ch6 Set CHTx/Ch6 & IT ROK Xmit Ch6 if Successful if Previously Failed Set ...
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... TxD FCS RxD INT Sleep Command TSS463-AA 52 Sleep, idle and activate commands are located in the Command Register (0x03). These three commands are general commands for the TSS463AA. After reset, the TSS463AA starts in idle mode. In this mode, the oscillator operates (CKOUT pin active) but the circuit cannot transmit or receive anything on the VAN bus. ...
Page 53
... All the others can be different between the two channels, for example the ID_Tag. The Channel j linked . . . . to the Channel i CHER CHTx CHRx i EXT RAK RNW RTR CHER CHTx CHRx Mess_Ptr EXT RAK RNW RTR TSS463-AA Channel i and j share the same Message area --- Message for Channels i & j --- DATA n DATA 0 Message Status 53 ...
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... Sleep Mode I is measured according CCSB 2. Active mode I is measured at: XTAL = 8 MHz clock, VAN speed rate = 125 KTS/s. CCOP function of the Clock Frequency. Figure 38 displays a graph showing RESET, RxD0, RxD1, RxD2 inputs. TSS463-AA 54 *NOTICE: +0. 10 Min. ...
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... Figure 37 Figure 38. I versus Clock Frequency at 125 KTimeslot/s CCOP mA 9 8.5 8 7.5 TSS463-AA MHz ...
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... AC Characteristics SS (INPUT) SCLK (INPUT) MISO (OUTPUT) MOSI (INPUT) INT TSS463- 10 -40°C to 125° Table 11. Microprocessor Interface C = 200pF on SPI/SCI Lines LOAD Symbol Characteristic Operating Frequency SPI f OP SCI Cycle Time SPI t CYC SCI t Enable Lead Time LEAD t Enable Lead Time ...
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... C1 (no capacitance needed) see Note: Symbol Parameter t Oscillator period CHCH t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL V IH XTAL1 TSS463-AA MHz Figure 5 Min Max 120 CHCL CLCH ...
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... Packaging Information SO16 TSS463- 2.35 A1 0.10 B 0.35 C 0.23 D 10.10 E 7.40 e 1.27 H 10.00 h 0. 0° 8° Inch 2.65 0.093 0.30 0.004 0.49 0.014 0.32 0.009 10.50 0.398 7.60 0.291 BSC 0.050 10.65 0.394 0.75 0.010 1.27 0.016 16 0° 8° 4205A–AUTO–03/03 0.104 0.012 0.019 0.013 0.413 0.299 BSC 0.419 0.029 ...
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... Ordering Information 4205A–AUTO–03/03 Part Number Supply Voltage TSS463-AA 5V +10% TSS463-AA +10% TSS463-AA Temperature Range Package -40°C to +125°C SO16 -40°C to +125°C SO16 Packing Stick Tape and Reel 59 ...
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... Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...