IDT7202 IDT [Integrated Device Technology], IDT7202 Datasheet - Page 11

• Manufacturer Part Number: IDT7202
• Description: CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
WIDTH EXPANSION CONFIGURATION
corresponding input control signals of multiple devices. Sta-
tus flags (
NOTE:
1. Flag detection is accomplished by monitoring the
DEPTH EXPANSION (DAISY CHAIN) MODE
tions when the requirements are for greater than 1K/2K/4K
words. Figure 15 demonstrates Depth Expansion using three
IDT72021/031/041s. Any depth can be attained by adding
additional devices. The IDT72021/031/041 operates in the
Depth Expansion configuration when the following conditions
are met:
1. The first device must be designed by grounding the First
2. All other devices must have
3. The Expansion Out (
4. External logic is needed to generate a composite Full
5. The Retransmit (
COMPOUND EXPANSION MODE
applied together in a straight forward manner to achieve large
FIFO arrays (see Figure 16).
Word width may be increased simply by connecting the
not connect any output signals together.
The IDT72021/031/041 can easily be adapted to applica-
The two expansion techniques described above can be
Load (
to the Expansion In (
Figure 15.
Flag (
of all
generate the correct composite
Figure 15.
not available in the Depth Expansion Mode. For addi-
tional information refer to Tech Note 9: “Cascading
FIFOs or FIFO Modules”.
FULL FLAG (FF)
EF
FF
FL
EF
s and ORing of all
) and Empty Flag (
RESET (RS)
DATA IN (D)
) control input.
,
WRITE (W)
FF
,
HF
Figure 14. Block Diagram of 1K/2K/4K x 18 FIFO Memory Used in Width Expansion Configuration
, and
RT
) function and Half-Full Flag (
XO
XI
AEF
18
) pin of the next device. See
) pin of each device must be tied
) can be detected from any one
FF
EF
FL
s (i.e. all must be set to
9
). This requires the ORing
in the HIGH state.
FF
72021/031/041
or
AEF
EF
FF
IDT
). See
,
EF
XI
HF
,
HF
and
HF
9
) are
AEF
9
signals on either (any) device used in the width expansion configuration. Do
5.09
device. Figure 14 demonstrates an 18-bit word width by using
two IDT72021/031/041 devices. Any word width can be at-
tained by adding additional IDT72021/031/041s.
BIDIRECTIONAL MODE
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT72021/031/041s as shown in
Figure 17. Care must be taken to assure that the appropriate
flag is monitored by each system (i.e.,
device where
R
be used in this mode.
DATA FLOW-THROUGH MODES
flow-through and write flow-through mode. For the read flow-
through mode (Figure 18), the FIFO permits the reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (t
edge of
the
would go into a three-state mode after t
would have a pulse showing temporary deassertion and then
would be asserted. In the interval of time that
more words can be written to the FIFO (the subsequent writes
after the first write edge will be deassert the Empty Flag);
however, the same word (written on the first write edge),
presented to the output bus as the read pointer, would not be
incremented when
words that are written to the FIFO will appear on the output bus
as in the read cycle timings.
72021/031/041
AEF
is used). Both Depth Expansion and Width Expansion may
Applications which require data buffering between two
Two types of flow-through modes are permitted: a read
R
IDT
line is raised from LOW-to-HIGH, after which the bus
W
HF
, called the first write edge. It remains on the bus until
XI
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
is used;
9
R
was LOW. On toggling
18
EF
is monitored on the device where
OUTPUT ENABLE (OE)
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
DATA OUT (Q)
WEF
FF
+ t
RHZ
A
is monitored on the
) ns after the rising
2677 drw 17
ns. The
R
R
, the other
was LOW,
EF
11
line