IDT7164 IDT [Integrated Device Technology], IDT7164 Datasheet - Page 8

• Manufacturer Part Number: IDT7164
• Description: CMOS STATIC RAM 64K (8K x 8-BIT)
• Manufacturer: IDT [Integrated Device Technology]

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
NOTES:
1.
2. A write occurs during the overlap of a LOW
3. t
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the
6.
7. Transition is measured 200mV from steady state.
ADDRESS
ADDRESS
DATA
WE
OE
I/O drivers to turn off and data to be placed on the bus for the required t
apply and the minimum write pulse width is as short as the specified t
WR1, 2
DATA
DATA
,
is continuously HIGH. If
CS
CS
CS
CS
CS
CS
WE
OUT
WE
is measured from the earlier of
1
IN
1
IN
2
1
or CS
2
1
LOW transition or CS
2
must be inactive during all address transitions.
(4)
OE
2
HIGH transition occurs simultaneously with or after the
is LOW during a
CS
t
AS
1
or
t
WE
WHZ
WE
t
AS
, a LOW
(7)
WE
going HIGH or CS
controlled write cycle, the write pulse width must be the larger of t
CS
1
t
AW
and a HIGH CS
(5)
2
t
going LOW to the end of the write cycle.
WP
AW
t
t
DW
WC
WE WE
WC
CS CS
6.1
.
. If
t
WP
2
CONTROLLED TIMING)
OE
.
CONTROLLED TIMING)
(6)
is HIGH during a
t
DW
WE
t
CW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW transition, the outputs remain in a high-impedance state.
DATA VALID
t
WE
DW
DATA VALID
controlled write cycle, this requirement does not
t
WR1 (3)
t
DH1, 2
t
OW (7)
t
DH1,2
(1, 2)
(1, 2, 6)
WP
t
t
WR2 (3)
WR1 (3)
or (t
WHZ
+t
DW
) to allow the
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