A43E06321G-75F AMICC [AMIC Technology], A43E06321G-75F Datasheet - Page 25

• Manufacturer Part Number: A43E06321G-75F
• Description: 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Read & Write Cycle at Same Bank @Burst Length=4
PRELIMINARY
(CL = 2)
(CL = 3)
CLOCK
A10/AP
ADDR
CKE
RAS
CAS
DQ
DQM
CS
DQ
BA
WE
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
0
Row Active
(A-Bank)
Ra
Ra
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
3. Access time from Row address. t
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
1
enters precharge. Last valid output will be Hi-Z after t
At Full page bit burst, burst is wrap-around.
(July, 2005, Version 0.0)
2
t
RCD
*Note 3
*Note 3
t
RAC
3
t
(A-Bank)
RAC
Ca0
Read
4
t
SAC
5
t
SAC
t
OH
Qa0
t
RC
6
t
*Note 1
OH
CC
Qa1
Qa0
*(t
7
RCD
Precharge
(A-Bank)
Qa2
Qa1
+ CAS latency-1) + t
8
*Note 2
t
SHZ
Qa3
Qa2
9
t
SHZ
24
High
Qa3
SHZ
*Note 4
10
Row Active
from the clock.
(A-Bank)
Rb
Rb
*Note 4
11
SAC
12
13
(A-Bank)
Db0
Db0
Write
Cb0
14
AMIC Technology, Corp.
Db1
Db1
15
Db2
Db2
16
t
t
RDL
RDL
Db3
Db3
17
A43E06321
18
Precharge
(A-Bank)
: Don't care
19