A43E06321G-75F AMICC [AMIC Technology], A43E06321G-75F Datasheet - Page 21

• Manufacturer Part Number: A43E06321G-75F
• Description: 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

12. About Burst Type Control
13. About Burst Length Control
PRELIMINARY
Random
Interrupt
Special
MODE
MODE
MODE
MODE
MODE
Basic
Basic
(Interrupted by Precharge)
Random column Access
(July, 2005, Version 0.0)
Sequential counting
Interleave counting
CAS
RAS Interrupt
t
CCD
BRSW
= 1 CLK
Interrupt
1
2
4
8
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “010”
At MRS A2,1,0 = “011”.
At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
t
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge,
RDL
= 2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
20
CAS
AMIC Technology, Corp.
interrupt can not be issued.
A43E06321