HFA3524IA96 INTERSIL [Intersil Corporation], HFA3524IA96 Datasheet - Page 9

• Manufacturer Part Number: HFA3524IA96
• Description: 2.5GHz/600MHz Dual Frequency Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

Functional Description
The simplified block diagram in Figure 14 shows the 22-bit
data register, two 15-bit R Counters and the 15-bit and 18-bit
N Counters (intermediate latches are not shown). The data
stream is clocked (on the rising edge of Clock) into the DATA
input, MSB first. The last two bits are the Control Bus. The
DATA is transferred into the counters as follows:
Programmable Reference Dividers (IF and RF R Counters)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets the
15-bit R Counter. Serial data format is shown below.
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
NOTES:
10. R1 to R15: These bits select the divide ratio of the programmable reference divider.
11. Data is shifted in MSB first.
8. Divide ratios less than 3 are prohibited.
9. Divide ratio: 3 to 32767.
CLOCK
DIVIDE
LSB
RATIO
OSC
32767
f
C1
IN
DATA
(Control bits)
f
IN
3
4
RF
LE
IF
IN
C2
15
R
0
0
1
PRESCALER
PRESCALER
R
1
OSC
RF
IF
R
2
14
R
0
0
1
R
3
13
9
R
0
0
1
R
4
N COUNTER
15-BIT IF
Divide ratio of the reference divider, R
12
N COUNTER
R
0
0
1
R
5
18-BIT RF
R COUNTER
R COUNTER
15-BIT RF
15-BIT IF
FIGURE 14. SIMPLIFIED BLOCK DIAGRAM
22-BIT DATA
R
6
REGISTER
11
R
0
0
1
R
7
10
R
0
0
1
R
8
HFA3524
R
9
0
0
1
R
9
10
R
PHASE
PHASE
COMP
COMP
R
8
0
0
1
LD
RF
LD
IF
11
R
C1
0
0
1
1
R
7
0
0
1
CONTROL BITS
12
R
CHARGE
CHARGE
PUMP
PUMP
13
R
R
6
0
0
1
14
R
C2
0
1
0
1
R
5
0
0
1
15
R
f
LOCK
DETECT
FASTLOCK
MUX
OUT
R
4
0
0
1
16
R
IR R Counter
RF R Counter
IF N Counter
RF N Counter
Program Modes
DATA LOCATION
17
R
R
3
0
1
1
18
R
D
F
D
R
2
1
0
1
O
O
O
/LD
IF
RF
19
R
MSB
R
1
1
0
1
20
R