HFA3524IA96 INTERSIL [Intersil Corporation], HFA3524IA96 Datasheet - Page 14

• Manufacturer Part Number: HFA3524IA96
• Description: 2.5GHz/600MHz Dual Frequency Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

Application Information
A block diagram of the basic phase locked loop is shown in
Figure 21.
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 22. The open loop
gain is the product of the phase comparator gain (K ), the
VCO gain (K
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 23, while
the complex impedance of the filter is given in Equation 2.
The time constants which determine the pole and zero
frequencies of the filter transfer function can be defined as:
and
Z s
T1
T2
Open loop gain
=
=
=
R2
R2 C2
R
---------------------------------------------------------------------------------- -
s
2
+
C1 C2 R2
--------------------- -
C1
C1 C2
I
-
REFERENCE
VCO
FIGURE 23. PASSIVE LOOP FILTER
CRYSTAL
+
FIGURE 22. PLL LINEAR MODEL
s C2 R2
=
=
C2
/s), and the loop filter gain Z(s) divided by
H(s) G(s)
K Z(s) K
E
D
O
C1
K
+
+
sC1
VCO
=
1
14
SYNTHESIZER
1/N
+
FREQUENCY
REFERENCE
I
Ns
sC2
Z(s)
DIVIDER
E
R2
C2
1/R
FIGURE 21. BASIC CHARGE PUMP PHASE LOCKED LOOP
VCO
K
VCO
s
f
f
P
R
f
FREQUENCY
REFERENCE
REF
DETECTOR
PHASE
(EQ. 3A)
(EQ. 3B)
O
(EQ. 1)
(EQ. 2)
HFA3524
R
P
DIVIDER
CHARGE
MAIN
PUMP
1/N
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, , the filter time constants T1 and T2,
and the design constants K K
From Equation 3 we can see that the phase term will be
dependent on the single pole and zero such that the phase
margin is determined in Equation 5.
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 24 with a solid trace. The parameter
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop
bandwidth, wp, the loop response time would be
approximately halved. Because the filter attenuation at the
comparison frequency also diminishes, the spurs would have
increased by approximately 6dB. In the proposed Fastlock
scheme, the higher spur levels and wider loop filter conditions
would exist only during the initial lock-on phase - just long
enough to reap the benefits of locking faster. The objective
would be to open up the loop bandwidth but not introduce any
additional complications or compromises related to our
original design criteria. We would ideally like to momentarily
shift the curve of Figure 24 over to a different cutoff frequency,
illustrated by the dotted line, without affecting the relative open
loop gain and phase relationships. To maintain the same
gain/phase relationship at twice the original cutoff frequency,
other terms in the gain and phase Equations 4 and 5 will have
to compensate by the corresponding “1/w” or 1/w
Examination of Equations 3 and 5 indicates the damping
resistor variable R2 could be chosen to compensate the “w”
terms for the phase margin. This implies that another resistor
G s
P
V
shows the amount of phase margin that exists at the point
P
=
H s
tan
D
f
O
IN
–
1
s = j w
FILTER
LOOP
T2
Z(s)
=
–
–
------------------------------------------------------------------ -
tan
K
2
–
C1 N 1
VCO
1
K
VCO
VCO
T1
1
+
+
+
, and N.
j
180
j
f
OUT
T1
o
T2
T1
------ -
T2
2
” factor.
(EQ. 4)
(EQ. 5)