HFA3524IA96 INTERSIL [Intersil Corporation], HFA3524IA96 Datasheet - Page 15

• Manufacturer Part Number: HFA3524IA96
• Description: 2.5GHz/600MHz Dual Frequency Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

of equal value to R2 will need to be switched in parallel with
R2 during the initial lock period. We must also insure that the
magnitude of the open loop gain, H(s)G(s) is equal to zero at
wp’ = 2wp. K
be changed by a factor of 4, to counteract the w
in the denominator of Equation 3. The K term was chosen to
complete the transformation because it can readily be
switched between 1X and 4X values. This is accomplished by
increasing the charge pump output current from 1mA in the
standard mode to 4mA in Fastlock.
Fastlock Circuit Implementation
A diagram of the Fastlock scheme as implemented in Intersil
Corporations HFA3524 PLL is shown in Figure 25. When a
new frequency is loaded, and the RF Icp
charge pump circuit receives an input to deliver 4 times the
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
VCO
REFERENCE
CRYSTAL
, K , N, or the net product of these terms can
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|<G(s) H(s)|
GAIN
0dB
15
REFERENCE
DIVIDER
1/R
FIGURE 25. FASTLOCK CIRCUIT IMPLEMENTATION
O
FIGURE 24. OPEN LOOP RESPONSE BODE PLOT
bit is set high, the
FASTLOCK
2
P
term present
f
f
R
DETECTOR
P
DIVIDER MAIN
PHASE
1/N
P
FREQUENCY
HFA3524
R
P
CHARGE
1X 4X
PUMP
normal current per unit phase error while an open drain
NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter
component values for the normal steady state
considerations. The device configuration ensures that as
long as a second identical damping resistor is wired in
appropriately, the loop will lock faster without any additional
stability considerations to account for. Once locked on the
correct frequency, the user can return the PLL to standard
low noise operation by sending an instruction with the RF
Icp
the loop filter capacitors and is enacted synchronous with
the charge pump output. This creates a nearly seamless
change between Fastlock and standard mode.
V
O
P
P ’
bit set low. This transition does not affect the charge on
F
D
O
f
O
LD
IN
P ’
= 2
LOOP FILTER
P
C1
R2’
PHASE
-90
-180
R2
C2
G(s) H(s)
VCO
RF
OUT