HFA3524IA96 INTERSIL [Intersil Corporation], HFA3524IA96 Datasheet - Page 11

• Manufacturer Part Number: HFA3524IA96
• Description: 2.5GHz/600MHz Dual Frequency Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

NOTES:
X = Don’t care condition
NOTES:
Phase Detector Polarity
Depending upon VCO characteristics, R16 bit should be set
accordingly, (see Figure 15).
• When VCO characteristics are positive like (1), R16
• When VCO characteristics are negative like (2), R16
16. The I
17. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective
18. When the F
19. Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the
20. The Fastlock mode utilizes the F
21. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits, the N counter resumes counting
0
1
should be set HIGH.
should be set LOW.
f
The R counter functionality does not become disabled until both IF and RF powerdown bits are activated. The OSC
pedance state when this condition exists. The control register remains active and capable of loading and latching in data during all of the pow-
erdown modes.
pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
of Fastlock occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated, the R counter is also forced
to Reset, allowing smooth acquisition upon powering up.
IN
RF R [19]
inputs (to a high impedance state). Powerdown forces the respective charge pump and phase comparator logic to a High Z State condition.
(RF LD)
CPO
POLARITY
X
X
X
X
0
0
1
1
0
0
1
1
1
Negative
Positive
LOW current state = 1/4 x I
O
D
/LD output is disabled, it is actively pulled to a low logic state.
Normal Operation
High Z State
D
11
O
IF R [19]
(IF LD)
HIGH Z STATE
O
0
1
0
1
0
0
1
1
0
1
0
1
1
/LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation
CPO
TABLE 3. THE F
HIGH current.
TABLE 2. MODE SELECT TRUTH TABLE
RF R [20]
(RF F
(NOTE 16)
O
0
0
0
0
0
1
0
1
1
1
1
1
1
HIGH
I
LOW
/LD (PIN 10) OUTPUT TRUTH TABLE
CPO
O
)
HFA3524
PRESCALER
IF R [20]
(IF F
16/17
0
0
0
0
1
0
1
0
1
1
1
1
1
8/9
IF
O
)
FIGURE 15. VCO CHARACTERISTICS
Disabled (Note 18)
IF Lock Detect (Note 19)
RF Lock Detect (Note 19)
RF/IF Lock Detect (Note 19)
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
Fastlock (Note 20)
For Internal Use Only
For Internal Use Only
For Internal Use Only
Counter Reset (Note 21)
VCO INPUT VOLTAGE
PRESCALER
32/33
64/65
RF
F
O
OUTPUT STATE
IN
pin reverts to a high im-
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(1)
(2)
POWERDOWN
(NOTE 17)