M25PX64-SOVME6F NUMONYX [Numonyx B.V], M25PX64-SOVME6F Datasheet - Page 13

• Manufacturer Part Number: M25PX64-SOVME6F
• Description: 64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface
• Manufacturer: NUMONYX [Numonyx B.V]

M25PX64
4
4.1
4.2
4.3
4.4
Operating features
Page programming
To program one data byte, two instructions are required: write enable (WREN), which is one
byte, and a page program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal program cycle (of duration t
To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from ‘1’ to ‘0’), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see
and
Dual input fast program
The dual input fast program (DIFP) instruction makes it possible to program up to 256 bytes
using two input pins at the same time (by changing bits from ‘1’ to ‘0’).
For optimized timings, it is recommended to use the dual input fast program (DIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several dual input fast program (DIFP) sequences each containing only a few bytes (see
Section 6.12: Dual input fast program
Subsector erase, sector erase and bulk erase
The page program (PP) instruction allows bits to be reset from ‘1’ to ’0’. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a subsector at a time, using the subsector erase (SSE) instruction, a sector
at a time, using the sector erase (SE) instruction, or throughout the entire memory, using the
bulk erase (BE) instruction. This starts an internal erase cycle (of duration t
The erase instruction must be preceded by a write enable (WREN) instruction.
Polling during a write, program or erase cycle
A further improvement in the time to write status register (WRSR), program OTP (POTP),
program (PP), dual input fast program (DIFP) or erase (SSE, SE or BE) can be achieved by
not waiting for the worst case delay (t
is provided in the status register so that the application program can monitor its value,
polling it to establish when the previous write cycle, program cycle or erase cycle is
complete.
Table 17: AC
characteristics).
W
(DIFP)).
, t
PP
, t
SSE
, t
SE
PP
, or t
).
BE
). The write in progress (WIP) bit
Page program (PP)
Operating features
SSE
, t
SE
or t
13/66
BE
).